Optically interconnected high bandwidth memory architectures

Abstract

A System-on-Chip (SoC) may be optically interconnected with memory. The SoC and a first electronic and photonic IC chip may be housed in a same semiconductor package. The first electronic and photonic IC chip may be in optical communication with a second electronic and photonic IC chip in electrical communication with memory. The first and second electronic and photonic IC chips may include microLEDs and photodetectors, for example bonded to surfaces of the first and second photonic IC chips. The optical communication may be through a transmission medium, which may be optical fibers. The optical fibers may be in one or more fiber bundles.

What is claimed is: 
     
         1 . A device including an optically connected high bandwidth memory, comprising:
 a first multi-chip package comprising a system-on-chip (SoC) and a first electronic and photonic integrated circuit chip on a first substrate, the SoC and the first electronic and photonic integrated circuit chip housed in a semiconductor package of the first multi-chip package, the first substrate including electrical pathways for electrical communication between the SoC and the first electronic and photonic circuit chip, the first electronic and photonic integrated circuit chip having a surface with an array of microLEDs and an array of photodetectors bonded thereto;   a second multi-chip package comprising a high bandwidth memory, a second electronic and photonic integrated circuit chip, and a memory controller, the high bandwidth and the second electronic and photonic integrated circuit chip housed in a semiconductor package of the second multi-chip package, the second electronic and photonic integrated circuit chip having a surface with an array of microLEDs and an array of photodetectors bonded thereto; and   
       an optical transmission medium coupling the first electronic and photonic integrated circuit chip and the second electronic and photonic integrated circuit chip. 
     
     
         2 . The device of  claim 1 , wherein the memory controller is part of the second electronic and photonic integrated circuit chip. 
     
     
         3 . The device of  claim 2 , wherein the second electronic and photonic integrated circuit chip and the high bandwidth memory are on a common substrate. 
     
     
         4 . The device of  claim 3 , wherein the common substrate is a silicon interposer. 
     
     
         5 . The device of  claim 4 , wherein the silicon interposer includes electrical signal pathways allowing for communication between the second electronic and photonic integrated circuit chip and the high bandwidth memory. 
     
     
         6 . The device of  claim 5 , wherein each of the second electronic and photonic integrated circuit chip and a buffer chip of the high bandwidth memory include die-to-die interface circuitry for communicating with each other over the electrical signal pathways of the silicon interposer. 
     
     
         7 . The device of  claim 3 , wherein the optical transmission medium comprises at least one optical fiber bundle. 
     
     
         8 . The device of  claim 2 , wherein the high bandwidth memory is on the second electronic and photonic integrated circuit chip. 
     
     
         9 . The device of  claim 1 , wherein the memory controller is part of buffer chip of the high bandwidth memory, and the high bandwidth memory is on the second electronic and photonic integrated circuit chip. 
     
     
         10 . The device of  claim 1 , wherein the second electronic and photonic integrated circuit chip are on an active silicon interposer. 
     
     
         11 . The device of  claim 10 , wherein the memory controller is part of the active silicon interposer.