1-bit 3-terminal racetrack array with integated magnetic tunnel junction (mtj)

Abstract

The present invention relates to racetrack memory array devices, and more specifically, to a manufacturing method of racetrack memory arrays with integrated magnetic tunnel junction for read/write.

1 . A memory array device including a racetrack (RT) layer, said memory array device having the following layer sequence starting from a substrate:
 the substrate,   a bottom metallization layer as a first metallization layer,   at least two functional layers including the RT layer and a magnetic tunnel junction (MTJ) layer, and   an outermost metallization layer as a second metallization layer.   
     
     
         2 . The memory array device according to  claim 1 , wherein the RT layer is next to the first metallization layer and the MTJ layer is next to the second metallization layer. 
     
     
         3 . The memory array device according to  claim 1 , wherein said memory array device additionally includes a barrier layer between the RT layer and the MTJ layer. 
     
     
         4 . The memory array device according to  claim 1, 3 , wherein the RT layer is based on a ferromagnetic structure or a synthetic antiferromagnetic structure. 
     
     
         5 . The memory array device according to  claim 4 , wherein the synthetic antiferromagnetic structure is comprised of two ferromagnetic layers coupled antiferromagnetically via a coupling layer. Page:  7   
     
     
         6 . The memory array device according to  claim 5 , wherein the coupling layer is comprised of a transition metal. 
     
     
         7 . The memory array device according to  claim 4 , wherein the ferromagnetic structure comprises one or more layers of a ferromagnetic material which is selected from one or more of Co, Ni, or Fe or an alloy of Fe and/or Co, or an alloy of Ni that may further include one or more of Fe and Co. 
     
     
         8 . The memory array device according to  claim 1 , wherein the RT layer has a total thickness in the range of 0.5 to 3.0 nm. 
     
     
         9 . The memory array device according to  claim 8 , wherein the RT layer includes multiple layers and each individual layer of the RT layer has a thickness in the range of 0.1 nm-1.5 nm. 
     
     
         10 . A process for manufacturing a memory array device according to  claim 1 , comprising the steps of
 providing a substrate;   covering the substrate with an insulating dielectric material thereby forming a structured substrate layer;   etching out positions for two electrodes on the insulating dielectric material on the structured substrate layer;   depositing a first metallic layer over the etched insulating dielectric material on the structured substrate layer;   planarizing the metallic layer, thereby creating two electrodes;   depositing at least two functional layers one after the other, wherein the functional layers are selected from a RT layer and a MTJ layer;   creating a mesa;   encapsulating the mesa with a barrier material, with the barrier material coplanar with a top layer of the functional layers, leaving the top layer of the functional layers exposed;   depositing a second metallic layer on the top layer of the functional layers thus creating a third electrode; and   etching the top layer of the functional layers and part of-the barrier material partially away so that the top layer of the functional layers is reduced to about the size of the third electrode.   
     
     
         11 . The process according to  claim 10 , wherein the depositing step comprises depositing the RT layer over the first metallic layer and depositing the MTJ layer on the RT layer. 
     
     
         12 . The process according to  claim 10 , wherein the process further comprises manufacturing a barrier layer between the RT layer and the MTJ layer. 
     
     
         13 . The memory array device according to  claim 7 , wherein the ferromagnetic structure comprises two or three layers of the ferromagnetic material.