High-Performance LDMOS Structures

Abstract

High-voltage transistors that may be fabricated in a standard low-voltage process. Embodiments include integrated circuits that combine, in a unitary structure, an LDMOS FET device that includes one or more dummy polysilicon structures (DPS's) overlying a drift region and comparable in configuration to the FET gate, and interstitial implant resistance pockets (IRP) formed within the drift region between the gate and an adjacent DPS and between each pair of adjacent DPS's. The IRPs may be augmented with floating contacts to remove heat from the drift region and provide additional shielding of the drain contact from the nearest edge of the gate. The IRPs may be biased to modulate the conductivity of the drift region. The DPS's may be biased to modulate the conductivity of the drift region, and in such a way as to protect each DPS from excessive and potentially destructive voltages.

1 . A high voltage switching device, including an integrated circuit that combines, in a unitary structure:
 (a) a transistor structure having a source, a channel adjacent the source, a gate structure over-laying the channel, and a drain spaced from the channel;   (b) an integrated, co-fabricated drift region formed between the channel and the drain;   (c) one or more dummy polysilicon structures formed overlaying the drift region between the gate structure and the drain, wherein a first dummy polysilicon structure is adjacent the gate structure; and   (d) at least one implant resistance pocket formed within the drift region and between the gate structure and the first dummy polysilicon structure.   
     
     
         2 . The invention of  claim 1 , wherein the first dummy polysilicon structure is adjacent to but spaced from the gate structure. 
     
     
         3 . The invention of  claim 1 , wherein there are at least two adjacent dummy polysilicon structures, further including, for each pair of adjacent dummy polysilicon structures, an implant resistance pocket formed within the drift region and between the pair of adjacent dummy polysilicon structures. 
     
     
         4 . The invention of  claim 1 , wherein the source and drain are doped with a first dopant, the drift region is doped with a second dopant, and the at least one implant resistance pocket is doped with a third dopant. 
     
     
         5 . The invention of  claim 1 , wherein the source and drain are N+ doped, the drift region is N doped, and each of the at least one implant resistance pocket are P doped. 
     
     
         6 . The invention of  claim 1 , wherein the source and drain are P+ doped, the drift region is P doped, and each of the at least one implant resistance pocket are N doped. 
     
     
         7 . The invention of  claim 1 , wherein the gate structure partially overlays the drift region. 
     
     
         8 . The invention of  claim 1 , wherein the gate structure includes doped polysilicon material. 
     
     
         9 . The invention of  claim 1 , wherein the one or more dummy polysilicon structures include undoped polysilicon material. 
     
     
         10 . The invention of  claim 1 , wherein the at least one implant resistance pocket is formed by implantation of a dopant. 
     
     
         11 . The invention of  claim 1 , wherein the at least one implant resistance pocket is formed by angled implantation of a dopant. 
     
     
         12 . The invention of  claim 1 , further including at least one floating contact formed over and in thermal contact with a corresponding implant resistance pocket of the at least one implant resistance pocket. 
     
     
         13 . The invention of  claim 1 , further including at least one electrical terminal in electrical contact with a corresponding dummy polysilicon structure of the one or more dummy polysilicon structures, wherein the dummy polysilicon structure having electrical terminals control the resistance of the drift region upon application of a bias voltage to the electrical terminals. 
     
     
         14 . The invention of  claim 1 , further including at least one electrical terminal in electrical contact with a corresponding implant resistance pocket of the at least one implant resistance pocket, wherein the implant resistance pockets having electrical terminals control the resistance of the drift region upon application of a bias voltage to the electrical terminals. 
     
     
         15 . The invention of  claim 1 , wherein the unitary structure is formed on a wafer including a substrate, a buried oxide layer formed on the substrate, and a silicon active layer formed on the buried oxide layer. 
     
     
         16 . The invention of  claim 1 , wherein the unitary structure is formed on a wafer including a substrate, a triple-well implant structure formed on the substrate, and a silicon active layer formed on the triple-well implant structure. 
     
     
         17 . A high voltage switching device, including an integrated circuit that combines, in a unitary structure:
 (a) a transistor structure having a source, a channel adjacent the source, a gate structure overlaying the channel, and a drain spaced from the channel;   (b) an integrated, co-fabricated drift region formed between the channel and the drain; and   (c) one or more dummy polysilicon structures formed overlaying the drift region between the gate structure and the drain, wherein a first dummy polysilicon structure is adjacent the gate structure.   
     
     
         18 . The invention of  claim 17 , wherein the first dummy polysilicon structure is adjacent to but spaced from the gate structure. 
     
     
         19 . The invention of  claim 17 , wherein the gate structure partially overlays the drift region. 
     
     
         20 . The invention of  claim 17 , wherein the one or more dummy polysilicon structures include undoped polysilicon material. 
     
     
         21 . The invention of  claim 17 , wherein the unitary structure is formed on a wafer including a substrate, a buried oxide layer formed on the substrate, and a silicon active layer formed on the buried oxide layer. 
     
     
         22 . The invention of  claim 17 , wherein the unitary structure is formed on a wafer including a substrate, a triple-well implant structure formed on the substrate, and a silicon active layer formed on the triple-well implant structure. 
     
     
         23 .- 25 . (canceled)