Method and apparatus for use in improving linearity of mosfets using an accumulated charge sink-harmonic wrinkle reduction

Abstract

A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

1 . (canceled) 
     
     
         2 . An accumulated charge control (ACC) transistor comprising:
 a drain;   a source;   a body having a channel region between the drain and the source;   a gate configured to receive a gate bias voltage such that a channel through which current passes between the source and the drain is selectively formed in the channel region of the body based at least on a voltage level of the gate bias voltage; and   an accumulated charge sink (ACS) region coupled to the body and configured to remove, via the ACS region, charge accumulated within the body of the ACC transistor to improve a linearity of the ACC transistor.   
     
     
         3 . The ACC transistor of  claim 2 , wherein the ACS region is configured to receive a bias voltage to remove the charge accumulated within the body via the ACS region. 
     
     
         4 . The ACC transistor of  claim 2 , wherein the ACS region is configured to receive a bias voltage to control charge that, without the bias voltage received, would accumulate in the body. 
     
     
         5 . The ACC transistor of  claim 2 , wherein the ACC transistor is configured to selectively operate in an on state or an off state, and wherein ACS region is configured to remove, via the ACS region during at least a portion of a duration when the ACC transistor is in the off state, the charge accumulated within the body of the ACC transistor. 
     
     
         6 . The ACC transistor of  claim 2 , wherein the ACC transistor is a metal-oxide-semiconductor field effect transistor. 
     
     
         7 . The ACC transistor of  claim 2 , wherein the ACS region is further coupled to the gate. 
     
     
         8 . The ACC transistor of  claim 2 , further comprising a diode coupled between the ACS region and the gate. 
     
     
         9 . The ACC transistor of  claim 2 , wherein the ACC transistor is configured to selectively operate in an on state or an off state, and wherein the charge accumulated within the body is associated with carriers having a polarity opposite of carriers in the drain and the source when the ACC transistor is operated in the on state. 
     
     
         10 . The ACC transistor of  claim 2 , wherein the ACS region is a first ACS region, wherein the ACC transistor further comprises a second ACS region coupled to the body and configured to remove, via the second ACS region, the charge accumulated within the body to improve the linearity of the ACC transistor. 
     
     
         11 . A switch comprising the ACC transistor of  claim 2 , the switch further comprising:
 a first port; and   a second port, wherein the ACC transistor is configured to selectively connect the first port to the second port.   
     
     
         12 . A method for operating a transistor, the method comprising:
 receiving, by an accumulated charge sink (ACS) region of the transistor, a bias voltage; and   removing, via the ACS region and based on the bias voltage, charge accumulated within a body of the transistor coupled to the ACS region to improve a linearity of the transistor.   
     
     
         13 . The method of  claim 12 , further comprising selectively operating the transistor in an on state or an off state, wherein the bias voltage is received during at least a portion of a duration when the transistor is in the off state. 
     
     
         14 . The method of  claim 12 , further comprising selectively operating the transistor in an on state or an off state, wherein the charge accumulated within the body is associated with carriers having a polarity opposite of carriers in a drain and a source of the transistor when the transistor is in the on state. 
     
     
         15 . The method of  claim 12 , wherein the ACS region is a first ACS region and the bias voltage is a first bias voltage, the method further comprising:
 receiving, by a second ACS region of the transistor, a second bias voltage; and   removing, via the second ACS region and based on the second bias voltage, the charge accumulated within the body of the transistor to improve the linearity of the transistor.   
     
     
         16 . The method of  claim 15 , further comprising shorting the first ACS region and the second ACS region by a structure coupled to the first ACS region and the second ACS region. 
     
     
         17 . An apparatus comprising:
 means for receiving a first bias voltage; and   means for removing charge accumulated within a body of a transistor based on the first bias voltage to improve a linearity of the transistor.   
     
     
         18 . The apparatus of  claim 17 , further comprising means for controlling the transistor to set the transistor to be in either an on state or an off state, wherein the means for removing comprises means for removing the charge accumulated within the body based on the first bias voltage during at least a portion of a duration when the transistor is in the off state. 
     
     
         19 . The apparatus of  claim 17 , wherein the charge accumulated within the body is associated with carriers having a polarity opposite of carriers in a drain and a source of the transistor when the transistor is in an on state. 
     
     
         20 . The apparatus of  claim 17 , further comprising means for selectively preventing current flow between the body and a gate of the transistor. 
     
     
         21 . The apparatus of  claim 17 , further comprising:
 means for receiving a second bias voltage; and   means for removing the charge accumulated within the body of the transistor based on the second bias voltage to improve the linearity of the transistor.