Wiring substrate and semiconductor package including the same

Abstract

A wiring substrate may include a core portion, an upper peripheral portion on a top surface of the core portion, and a lower peripheral portion on a bottom surface of the core portion. The upper peripheral portion may include a bridge chip provided on the top surface of the core portion, upper insulating patterns provided on the top surface of the core portion to cover the bridge chip, and upper interconnection patterns in the upper insulating patterns. The lower peripheral portion may include a dummy structure on the bottom surface of the core portion, lower insulating patterns on the bottom surface of the core portion to cover the dummy structure, and lower interconnection patterns in the lower insulating patterns. A mean thermal expansion coefficient of the upper peripheral portion may be substantially equal to a mean thermal expansion coefficient of the lower peripheral portion.

What is claimed is: 
     
         1 . A wiring substrate, comprising:
 a core portion;   an upper peripheral portion provided on a top surface of the core portion; and   a lower peripheral portion provided on a bottom surface of the core portion,   wherein the core portion comprises a penetration via vertically penetrating the core portion and electrically connecting the upper peripheral portion to the lower peripheral portion,   wherein the upper peripheral portion comprises:
 a bridge chip provided on the top surface of the core portion; 
 upper insulating patterns provided on the top surface of the core portion and covering the bridge chip; and 
 upper interconnection patterns in the upper insulating patterns, 
   wherein the lower peripheral portion comprises:
 a dummy structure provided on the bottom surface of the core portion; 
 lower insulating patterns provided on the bottom surface of the core portion and covering the dummy structure; and 
 lower interconnection patterns in the lower insulating patterns, 
   wherein a mean thermal expansion coefficient of the upper peripheral portion is substantially equal to a mean thermal expansion coefficient of the lower peripheral portion.   
     
     
         2 . The wiring substrate of  claim 1 , wherein a thermal expansion coefficient of the dummy structure is between 0.9 and 1.1 times a thermal expansion coefficient of the bridge chip. 
     
     
         3 . The wiring substrate of  claim 2 , wherein the thermal expansion coefficient of the bridge chip is substantially equal to the thermal expansion coefficient of the dummy structure. 
     
     
         4 . The wiring substrate of  claim 1 , wherein a main material of the bridge chip is substantially the same as a main material of the dummy structure. 
     
     
         5 . The wiring substrate of  claim 1 , wherein the bridge chip and the dummy structure have substantially the same shape. 
     
     
         6 . The wiring substrate of  claim 1 , wherein a side surface of the bridge chip and a side surface of the dummy structure are aligned with each other in a direction perpendicular to the top surface of the core portion. 
     
     
         7 . The wiring substrate of  claim 1 , wherein the bridge chip overlaps with the dummy structure. 
     
     
         8 . The wiring substrate of  claim 1 , further comprising a first adhesive layer attaching the bridge chip to the top surface of the core portion. 
     
     
         9 . The wiring substrate of  claim 1 , further comprising a second adhesive layer attaching the dummy structure to the bottom surface of the core portion. 
     
     
         10 . The wiring substrate of  claim 1 , wherein the penetration via is shifted from the bridge chip in a direction parallel to the top surface of the core portion. 
     
     
         11 . A wiring substrate, comprising:
 a first redistribution layer;   a second redistribution layer provided on the first redistribution layer;   a core portion disposed between the first redistribution layer and the second redistribution layer, the core portion comprising a center region and peripheral regions enclosing the center region;   a dummy chip provided on the center region of the core portion and in the first redistribution layer; and   a bridge chip provided on the center region of the core portion and in the second redistribution layer,   wherein a thermal expansion coefficient of the dummy chip is between 0.9 and 1.1 times a thermal expansion coefficient of the bridge chip.   
     
     
         12 . The wiring substrate of  claim 11 , further comprising a penetration viain the peripheral regions of the core portion that penetrate the core portion and electrically connects the first redistribution layer to the second redistribution layer. 
     
     
         13 . The wiring substrate of  claim 11 , wherein the bridge chip comprises:
 a bridge substrate; and   a bridge interconnection layer on a top surface of the bridge substrate,   wherein the bridge interconnection layer comprises bridge circuit patterns.   
     
     
         14 . The wiring substrate of  claim 11 , further comprising a first adhesive layer attaching the bridge chip to a top surface of the core portion. 
     
     
         15 . The wiring substrate of  claim 11 , further comprising a second adhesive layer attaching the dummy chip to a bottom surface of the core portion. 
     
     
         16 . The wiring substrate of  claim 11 , wherein the first redistribution layer comprises:
 first substrate insulating patterns covering the bottom surface of the core portion; and   first interconnection patterns in the first substrate insulating patterns,   wherein the second redistribution layer comprises:   second substrate insulating patterns covering the top surface of the core portion; and   second interconnection patterns in the second substrate insulating patterns.   
     
     
         17 . The wiring substrate of  claim 16 , wherein, on the top surface of the core portion, the second substrate insulating patterns cover the bridge chip, and
 the second interconnection patterns are electrically connected to the circuit patterns of the bridge chip.   
     
     
         18 . The wiring substrate of  claim 16 , wherein, in the first substrate insulating patterns, the dummy chip and the first substrate interconnection patterns are horizontally spaced apart from each other, and the dummy chip is in an electrically floated state. 
     
     
         19 . The wiring substrate of  claim 16 , wherein, on the bottom surface of the core portion, the first substrate insulating pattern covers the dummy chip. 
     
     
         20 . A semiconductor package, comprising:
 a package substrate;   a first semiconductor chip on the package substrate;   a chip stack provided on the package substrate, wherein the chip stack is laterally spaced apart from the first semiconductor chip, wherein the chip stack comprising a plurality of second semiconductor chips that are vertically stacked; and   a mold layer provided on the substrate to enclose the first semiconductor chip and the chip stack,   wherein the package substrate comprises:   a core portion;   a bridge chip provided on a top surface of the core portion;   an upper peripheral portion covering the top surface of the core portion and the bridge chip;   a dummy structure provided on a bottom surface of the core portion; and   a lower peripheral portion covering the bottom surface of the core portion and the dummy structure,   wherein a material of the bridge chip is substantially the same as a material of the dummy structure, and   the bridge chip and the dummy structure overlap each other.