Wafer double-side polishing apparatus and method of evaluating the same

Abstract

A wafer double-side polishing apparatus is disclosed. The wafer double-side polishing apparatus includes an upper plate and a lower plate facing each other, polishing pads respectively disposed at a lower portion of the upper plate and at an upper portion of the lower plate, a first gear disposed in a central region of an upper surface of the lower plate, a second gear disposed in a peripheral region of the upper surface of the lower plate, and carriers disposed between the polishing pads while being engaged between the first gear and the second gear. The upper plate includes a plurality of slurry supply holes extending in a vertical direction. Each of the carriers includes at least one wafer accommodation hole. The sum of cross-sectional areas of the wafer accommodation holes of the carriers is 32 to 34% of the cross-sectional area of the lower plate.

What is claimed is: 
     
         1 . A wafer double-side polishing apparatus comprising:
 an upper plate and a lower plate facing each other;   polishing pads respectively disposed at a lower portion of the upper plate and at an upper portion of the lower plate;   a first gear disposed in a central region of an upper surface of the lower plate and a second gear disposed in a peripheral region of the upper surface of the lower plate; and   carriers disposed between the polishing pads while being engaged between the first gear and the second gear,   wherein the upper plate comprises a plurality of slurry supply holes extending in a vertical direction,   wherein each of the carriers comprises at least one wafer accommodation hole, and   wherein a sum of cross-sectional areas of the wafer accommodation holes of the carriers is 32 to 34% of a cross-sectional area of the lower plate.   
     
     
         2 . The wafer double-side polishing apparatus according to  claim 1 , wherein:
 the carriers have a same shape, and the at least one wafer accommodation hole of each carrier comprises three wafer accommodation holes; and   the carriers comprise five carriers engaged between the first gear and the second gear.   
     
     
         3 . The wafer double-side polishing apparatus according to  claim 1 , wherein:
 the carriers have a same shape, and the at least one wafer accommodation hole of each carrier comprises four wafer accommodation holes; and   the carriers comprise four carriers engaged between the first gear and the second gear.   
     
     
         4 . The wafer double-side polishing apparatus according to  claim 1 , wherein slurry supplied to the slurry supply holes comprises silica particles having a size of 40 to 100 nanometers. 
     
     
         5 . The wafer double-side polishing apparatus according to  claim 2 , wherein slurry supplied to the slurry supply holes comprises silica particles having a size of 40 to 100 nanometers. 
     
     
         6 . The wafer double-side polishing apparatus according to  claim 3 , wherein slurry supplied to the slurry supply holes comprises silica particles having a size of 40 to 100 nanometers. 
     
     
         7 . The wafer double-side polishing apparatus according to  claim 4 , wherein a pH of the slurry is 11 or more. 
     
     
         8 . The wafer double-side polishing apparatus according to  claim 4 , wherein a particle concentration of the slurry is 1 to 1.5%. 
     
     
         9 . The wafer double-side polishing apparatus according to  claim 4 , wherein each of the polishing pads has a hardness of 83 to 93 HRC. 
     
     
         10 . The wafer double-side polishing apparatus according to  claim 4 , wherein each of the polishing pads has a compressiveness of 0.7 to 3.1%. 
     
     
         11 . The wafer double-side polishing apparatus according to  claim 1 , wherein wafers are accommodated in the wafer accommodation holes of the carriers, respectively, and the lower plate and the upper plate are pressurized by force of 100 to 160 g/cm 2 . 
     
     
         12 . The wafer double-side polishing apparatus according to  claim 2 , wherein wafers are accommodated in the wafer accommodation holes of the carriers, respectively, and the lower plate and the upper plate are pressurized by force of 100 to 160 g/cm 2 . 
     
     
         13 . The wafer double-side polishing apparatus according to  claim 3 , wherein wafers are accommodated in the wafer accommodation holes of the carriers, respectively, and the lower plate and the upper plate are pressurized by force of 100 to 160 g/cm 2 . 
     
     
         14 . A wafer double-side polishing apparatus evaluation method comprising:
 preparing a wafer double-side polishing apparatus comprising an upper plate and a lower plate facing each other, polishing pads respectively disposed at a lower portion of the upper plate and at an upper portion of the lower plate, a first gear disposed in a central region of an upper surface of the lower plate, a second gear disposed in a peripheral region of the upper surface of the lower plate, and carriers disposed between the polishing pads while being engaged between the first gear and the second gear, the upper plate comprising a plurality of slurry supply holes extending in a vertical direction, each of the carriers comprising at least one wafer accommodation hole;   accommodating wafers in the wafer accommodation holes of the carriers, respectively, supplying slurry through the slurry supply holes, and polishing the wafers by friction thereof with the polishing pads disposed pads disposed thereover and thereunder; and   comparing a B/A value with a global backside ideal plane range (GBIR),   wherein “A” is a cross-sectional area of the lower plate, “B” is a sum of cross-sectional areas of the wafer accommodation holes formed at the carriers, and “GBIR” represents a height difference between a highest portion and a lowest portion of a surface of each wafer.   
     
     
         15 . The wafer double-side polishing apparatus evaluation method according to  claim 14 , wherein carriers each formed with wafer accommodation holes and lower plates configured to support corresponding ones of the carriers and to satisfy different B/A values of 25%, 31%, 33%, and 35%, together with the corresponding carriers, respectively, are prepared. 
     
     
         16 . The wafer double-side polishing apparatus evaluation method according to  claim 14 , wherein:
 carriers having a same shape, each of the carriers having three wafer accommodation holes, are prepared; and   the carriers comprise five carries engaged between the first gear and the second gear.   
     
     
         17 . The wafer double-side polishing apparatus evaluation method according to  claim 14 , wherein:
 carriers having a same shape, each of the carriers having four wafer accommodation holes, are prepared; and   the carriers comprise four carries engaged between the first gear and the second gear.   
     
     
         18 . The wafer double-side polishing apparatus evaluation method according to  claim 14 , wherein, in the polishing, the lower plate and the upper plate are pressurized by force of 100 to 160 g/cm 2 . 
     
     
         19 . The wafer double-side polishing apparatus evaluation method according to  claim 14 , wherein, in the polishing, the slurry supplied to the slurry supply holes comprises silica particles having a size of 40 to 100 nanometers, a pH of the slurry is 11 or more, and a particle concentration of the slurry is 1 to 1.5%. 
     
     
         20 . The wafer double-side polishing apparatus evaluation method according to  claim 14 , wherein polishing pads each having a hardness of 83 to 93 HRC and a compressiveness of 0.7 to 3.1% are prepared.