Semiconductor device and method of manufacturing semiconductor device
Abstract
An object is to provide a technology that can suppress a failure of embedding a metal layer in recesses of an alloy layer to improve the adhesive strength between the metal layer and the alloy layer. A semiconductor device includes: a semiconductor substrate; an alloy layer on the semiconductor substrate, the alloy layer containing a semiconductor material of the semiconductor substrate as a main component; and a metal layer on the alloy layer. A plurality of recesses is discretely formed in a surface of the alloy layer which is closer to the metal layer, and 90% or more of the recesses have a bowl shape which monotonously decreases as an opening width of each of the recesses proceeds to a depth portion of the recess.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device, comprising:
a semiconductor substrate; an alloy layer on the semiconductor substrate, the alloy layer containing a semiconductor material of the semiconductor substrate as a main component; and a metal layer on the alloy layer, wherein a plurality of recesses is discretely formed in a surface of the alloy layer which is closer to the metal layer, and 90% or more of the recesses have a bowl shape which monotonously decreases as an opening width of each of the recesses proceeds to a depth portion of the recess.
2 . The semiconductor device according to claim 1 ,
wherein the opening width of each of the recesses is 5 nm or more and 100 nm or less, the alloy layer has a thickness of 30 nm or more, and a depth of each of the recesses is less than the thickness of the alloy layer.
3 . The semiconductor device according to claim 1 , further comprising
an interlayer insulating film on the semiconductor substrate, the interlayer insulating film including a contact region, wherein a bottom width of the contact region is 0.2 μm or more and 1.0 μm or less.
4 . The semiconductor device according to claim 3 ,
wherein a ratio of the bottom width of the contact region to a thickness of the interlayer insulating film is 1.5 or more.
5 . The semiconductor device according to claim 1 ,
wherein a concentration of an inert gas contained at an interface between the metal layer and the alloy layer is less than or equal to a concentration of an inert gas contained in a bulk of the semiconductor substrate.
6 . The semiconductor device according to claim 5 ,
wherein the inert gas contained at the interface between the metal layer and the alloy layer and the inert gas contained in the bulk of the semiconductor substrate are Ar or N 2 .
7 . The semiconductor device according to claim 1 ,
wherein an atomic density of an element contained in the alloy layer is 99.0 wt % or more.
8 . The semiconductor device according to claim 1 ,
wherein the metal layer is made of a metal containing TiN or Al as a main component, or made of a laminated metal including a metal containing TiN as a main component and a metal containing Al as a main component.
9 . The semiconductor device according to claim 1 ,
wherein the semiconductor device is a power semiconductor device, and the semiconductor material of the semiconductor substrate is Si, SiC, or a compound containing Ga.
10 . The semiconductor device according to claim 1 ,
wherein the alloy layer is made of silicide containing Ti or Ni.
11 . A method of manufacturing a semiconductor device, the method comprising:
depositing a metal on a semiconductor substrate by sputtering or chemical vapor deposition to form a metal film, the metal containing an inert gas; subjecting the metal film to a heat treatment to form an alloy layer; forming, in a surface of the alloy layer which is opposite to the semiconductor substrate, a region of a decreasing atomic density of metal atoms containing the inert gas or semiconductor atoms; etching the surface of the alloy layer to change the region of the decreasing atomic density into a recessed region with a plurality of recesses; and depositing, on the alloy layer including the recessed region, a metal to be a metal layer.Join the waitlist — get patent alerts
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