Integrated circuits devices, systems and methods

Abstract

A method can include receiving a first power supply voltage at a first terminal at a first side of an IC device and providing a row of stacked pairs of insulated gate field effect transistor (IGFETs) substantially at the second side of the IC device. Each stacked pair can include a first and second IGFET of different conductivity types. Each IGFET can include multiple channels and a control gate that substantially surrounds the channels. A first power supply can be coupled from the first power supply terminal to a first source of one IGFET of the stacked pair via a first conductive via disposed between the first side and the second side and a first conductive line buried in and proximate the second side below the row of stacked pairs. Corresponding devices and systems are also disclosed.

1 . A method, comprising:
 receiving a first power supply voltage at a first terminal substantially at a first side of an IC device;   providing at least one row of stacked pairs of insulated gate field effect transistor (IGFETs) disposed in a first direction substantially at the second side of the IC device, each stacked pair including a first IGFET and a second IGFET formed below the first IGFET of the respective stacked pair, each first and second IGFET including
 a first source/drain (S/D) and a second S/D, 
 a plurality channels disposed between the first and second S/D of the respective IGFET in a second direction that is substantially perpendicular to the first direction, and 
 a control gate that substantially surrounds the plurality of channels of the respective IGFET, the plurality of channels providing a controllable impedance path between a first and second S/D of the respective IGFET 
   coupling the first power supply voltage from the first terminal to the second side with a first conductive via disposed between the first side and the second side;   coupling the first power supply voltage from the first conductive via to a first conductive line buried in and proximate the second side below the at least one row of stacked pairs; and   coupling the first power supply voltage from the first conductive line to the first S/Ds of two first IGFETs of adjacent stacked pairs with a same first supply contact; wherein   the first IGFETs have a first conductivity type and the second IGFETs have a second conductivity type.   
     
     
         2 . The method of  claim 1 , further including:
 coupling a second power supply voltage to the first S/Ds of two second IGFETs of adjacent stacked pairs with a same second supply contact.   
     
     
         3 . The method of  claim 1 , wherein:
 the first supply contact is formed substantially over the second supply contact.   
     
     
         4 . The method of  claim 1 , wherein:
 the first supply contact is formed above, but not over the second supply contact.   
     
     
         5 . The method of  claim 1 , wherein:
 providing a second row of stacked pairs of IGFETs adjacent to the row of stacked pairs; and   coupling the first power supply voltage from the first conductive line to two first IGFETs of the first row of stacked pairs and to two first IGFETs of the second row of stacked pairs with a same conductive contact.   
     
     
         6 . The method of  claim 1 , further including:
 receiving a second power supply voltage at a second terminal substantially at the first side of an IC device;   coupling the second power supply voltage from the second terminal to the second side with a second conductive via disposed between the first side and the second side;   coupling the second power supply voltage from the second conductive via to a second conductive line buried in and proximate the second side below the at least one row of stacked pairs; and   coupling the second power supply voltage from the second conductive line to the first S/D of at least one IGFET in the row of stacked pairs.   
     
     
         7 . The method of  claim 1 , further including:
 forming at least one circuit with IGFETs from the at least one row of stacked pairs;   receiving an input signal at an input terminal substantially at the first side of the IC device;   coupling the input signal from the input terminal to the second side with an input conductive via disposed between the first side and the second side;   coupling the input signal from the input conductive via to an input conductive structure buried in and proximate the second side below the at least one row of stacked pairs; and   coupling the input signal to the at least one circuit from the input conductive structure.   
     
     
         8 . The method of  claim 1 , further including:
 generating an output signal with a circuit that includes at least one IGFET from the at least one row of stacked pairs;   coupling the output signal from the circuit to an output conductive structure buried in and proximate the second side below the at least one row of stacked pairs;   coupling the output signal from the output conductive structure to the first side with an output conductive via disposed between the second side and the first side; and   coupling the output signal from the output conductive via to an output terminal substantially at the first side.   
     
     
         9 . The method of  claim 8 , further including:
 coupling the output signal from the output conductive via to the output terminal with an output driver circuit formed substantially at the first side.   
     
     
         10 . The method of  claim 1 , further including:
 forming the first conductive line in a second surface of a substrate;   forming the first conductive via from a first surface of the substrate through the substrate to make electrical contact with the first conductive line, the first surface opposite the second surface; and   forming a resistor that includes at least a portion of the first surface.   
     
     
         11 . The method of  claim 1 , further including:
 forming the first conductive line in a second surface of a substrate; and   forming the first conductive via from a first surface of the substrate through the substrate to make electrical contact with the first conductive line, the first conductive via including a resistor.   
     
     
         12 . The method of  claim 1 , further including:
 providing a dummy conductive structure buried in and proximate the first side below the at least one row of stacked pairs;   transferring heat from the dummy conductive structure to a dummy via that extends from the second side to the first side; and   transferring heat from the dummy via to a heat sink structure substantially at the first side.   
     
     
         13 . The method of  claim 1 , wherein:
 the at least one row of stacked pairs is formed above a substrate; wherein   the plurality of channels are selected from the group of: parallel nanosheets, nanowires and fin structures the extend upward from a surface of the substrate.   
     
     
         14 . The method of  claim 1 , further including:
 forming at least one circuit element substantially at the first side.   
     
     
         15 . The method of  claim 14 , wherein:
 the at least one circuit element is selected from the group of: a capacitor, an inductor, and a resistor.   
     
     
         16 . The method of  claim 14 , wherein:
 the at least one circuit element comprises a power gating circuit configured to selectively electrically connect the first terminal to the first conductive via.   
     
     
         17 . The method of  claim 14 , wherein:
 the at least one circuit element comprises an output driver circuit.   
     
     
         18 . The method of  claim 1 , further including:
 providing at least one row of stacked pairs includes
 forming a first row of stacked pairs, 
 forming a second row of stacked pairs adjacent to the first row of stacked pairs, 
 forming a third row of stacked pairs adjacent to the second row of stacked pairs, and not adjacent to the first row of stacked pairs, forming a first contact having a conductive connection to 
 a first S/D of a first IGFET in the first row of stacked pairs, 
 a first S/D of a first IGFET in the second row of stacked pairs, and 
 the first conductive line. 
   
     
     
         19 . The method of  claim 1 , further including:
 forming a power supply distribution network at the second side comprising a conductive pattern that conductively connects the at least first terminal to the first conductive via.   
     
     
         20 . The method of  claim 1 , further including:
 providing at least one electrostatic discharge structure proximate the first side and electrically connected to at least the first terminal.