Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor package includes a semiconductor chip including a substrate, an interconnection structure on a front surface of the substrate, and a pad layer on a front surface of the interconnection structure. A first side surface of the semiconductor chip from a point on a side surface of the substrate to an edge of a front surface of the semiconductor chip is oblique to, or more curved than, the front surface of the semiconductor chip, and is oblique to, or more curved than, a second side surface of the semiconductor chip from the point to an edge of a back surface of the semiconductor chip.

1 . A semiconductor device comprising:
 a semiconductor chip including a substrate, an interconnection structure on a front surface of the substrate, and a pad layer on a front surface of the interconnection structure,   wherein, as viewed from a cross-section, a first side surface of the semiconductor chip from a point on a side surface of the substrate to an edge of a front surface of the semiconductor chip is oblique to, or more curved than, the front surface of the semiconductor chip, and is oblique to, or more curved than, a second side surface of the semiconductor chip from the point to an edge of a back surface of the semiconductor chip.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the side surface of the substrate has an angular shape at the point. 
     
     
         3 . The semiconductor device of  claim 2 , wherein:
 the first side surface of the semiconductor chip is flat-shaped from the point to the edge of the front surface of the semiconductor chip, and   the second side surface of the semiconductor chip is flat-shaped from the point to the edge of the back surface of the semiconductor chip.   
     
     
         4 . The semiconductor device of  claim 3 , wherein roughness of the first side surface of the semiconductor chip is rougher than roughness of the second side surface of the semiconductor chip. 
     
     
         5 . The semiconductor device of  claim 3 , wherein in a horizontal direction of the semiconductor chip, a maximum width component of the first side surface of the semiconductor chip is greater than 3 μm and less than 100 μm, and
 in a vertical direction of the semiconductor chip, a maximum height component of the first side surface of the semiconductor chip is greater than 10 μm and less than 300 μm. 
 
     
     
         6 . The semiconductor device of  claim 1 , wherein a maximum width component of the first side surface of the semiconductor chip in a horizontal direction of the semiconductor chip is greater than 0.1 times and less than 1 times a maximum height component of the first side surface of the semiconductor chip in a vertical direction of the semiconductor chip. 
     
     
         7 . The semiconductor device of  claim 1 , further including a plurality of memory chips on a front surface of the pad layer so that at least portions of respective memory chips overlap each other in a vertical direction,
 each of the plurality of memory chips includes a memory cell layer having memory cells,   among the plurality of memory chips, a memory chip closest to the pad layer further includes a bonding metal layer disposed between the memory cell layer and the semiconductor chip, and   a front surface of the semiconductor device is a front surface of a memory chip located furthest from the pad layer among the plurality of memory chips.   
     
     
         8 . The semiconductor device of  claim 1 , further including a memory chip on a front surface of the pad layer,
 wherein the memory chip includes,
 a memory cell layer having memory cells; and 
 a bonding metal layer between the memory cell layer and the semiconductor chip, and 
 the front surface of the semiconductor device is the front surface of the memory chip. 
   
     
     
         9 . The semiconductor device of  claim 8 , further comprising a connection pad on the memory chip,
 wherein the memory cell layer includes a plate layer electrically connected to the connection pad, gate electrodes stacked on a lower surface of the plate layer and spaced apart from each other in a first direction, perpendicular to the lower surface of the plate layer, and electrically connected to the bonding metal layer, and vertical channel structures extending in the first direction while penetrating through the gate electrodes and electrically connected to the bonding metal layer.   
     
     
         10 . The semiconductor device of  claim 1 , including a plurality of semiconductor chips connected to each other through direct bonding, and
 for each semiconductor chip of the semiconductor chips, a first side surface from a point on a side surface of a substrate of the semiconductor chip to an edge of a front surface of the semiconductor chip is oblique to, or more curved than, a second side surface from the point on the side surface of the substrate of the semiconductor chip to an edge of a back surface of the semiconductor chip.   
     
     
         11 . The semiconductor device of  claim 1 , wherein:
 the interconnection structure includes an interconnection line and an interconnection insulating layer,   the pad layer includes a pad and a pad insulating layer, and   each of the interconnection insulating layer and the pad insulating layer includes at least one of SiO 2 , SiN, SiCN, and tetraethyloxysilane (TEOS).   
     
     
         12 . The semiconductor device of  claim 11 , wherein the first side surface of the semiconductor chip has a heat affected zone, and
 the point is a bottommost point of the heat affected zone.   
     
     
         13 . The semiconductor device of  claim 12 , wherein in at least a portion of the heat affected zone, at least one of SiO 2 , SiN, SiCN and TEOS is mixed with a metallic material. 
     
     
         14 . A semiconductor package comprising:
 a semiconductor chip including a substrate, an interconnection structure disposed on a front surface of the substrate, and a pad layer disposed on a front surface of the interconnection structure,   wherein, as viewed from a cross-section, a first side surface of the semiconductor chip from a point on a side surface of the substrate to an edge of a front surface of the semiconductor chip has a heat affected zone,   wherein the point is a bottom of the heat affected zone.   
     
     
         15 . The semiconductor package of  claim 14 , wherein, as viewed from the cross-section, a second side surface of the semiconductor chip from the point to an edge of a back surface of the semiconductor chip does is not a heat affected zone, and wherein roughness of the first side surface of the semiconductor chip is rougher than roughness of the second side surface of the semiconductor chip. 
     
     
         16 . (canceled) 
     
     
         17 . The semiconductor package of  claim 14 , wherein in at least a portion of the heat affected zone, an insulating material and a metallic material are mixed with each other. 
     
     
         18 . The semiconductor package of  claim 14 , wherein a width of the heat affected zone increases from a point on the side surface of the substrate toward the edge of the front surface of the semiconductor chip, and wherein the heat affected zone runs continuously from the point to the edge of the front surface of the semiconductor chip. 
     
     
         19 . (canceled) 
     
     
         20 . The semiconductor package of  claim 14 , further including a plurality of memory chips disposed on a front surface of the pad layer so that at least portions of respective memory chips overlaps each other in a vertical direction,
 each of the plurality of memory chips includes a memory cell layer having memory cells,   among the plurality of memory chips, a memory chip disposed closest to the pad layer further includes a bonding metal layer disposed between a memory cell layer and the semiconductor chip, and   the front surface of the semiconductor package is a front surface of a memory chip located furthest from the pad layer among the plurality of memory chips.   
     
     
         21 . The semiconductor package of  claim 14 , further including:
 a memory chip on a front surface of the pad layer; and   a connection pad on the memory chip,   wherein the memory chip includes,
 a memory cell layer having memory cells; and 
 a bonding metal layer between the memory cell layer and the semiconductor chip, 
 wherein the front surface of the semiconductor package is a front surface of the memory chip, and wherein the memory cell layer includes a plate layer electrically connected to the connection pad, gate electrodes stacked on a lower surface of the plate layer and spaced apart from each other in a first direction, perpendicular to the lower surface of the plate layer, and electrically connected to the bonding metal layer, and vertical channel structures extending in the first direction while penetrating through the gate electrodes and electrically connected to the bonding metal layer. 
   
     
     
         22 . (canceled) 
     
     
         23 . The semiconductor package of  claim 14 , including a plurality of semiconductor chips connected to each other through direct bonding, and
 for each semiconductor chip of the plurality of semiconductor chips, a first side surface from a point on a side surface of a substrate of the semiconductor chip to an edge of a front surface of the semiconductor chip is oblique to, or more curved than, a second side surface from a point on the side surface of the substrate of the semiconductor chip to an edge of a back surface of the semiconductor chip.   
     
     
         24 - 30 . (canceled)