Memory cell of dynamic random access memory, array, memory, and device

Abstract

A memory cell of a dynamic random access memory, an array, a memory, and a device are provided. The memory cell includes a write word line, a write bit line, a write transistor, a read word line, a read bit line and a read transistor. The read transistor includes multiple channel layers composed of different materials. A gate electrode, a first electrode and a second electrode of the write transistor are connected to the write word line, the write bit line and a gate electrode of the read transistor respectively. The first and second electrodes of the write transistor are respectively source and drain electrodes of the write transistor. First and second electrodes of the read transistor are connected to the read bit line and the read word line respectively. The first and second electrodes of the read transistor are respectively source and drain electrodes of the read transistor.

What is claimed is: 
     
         1 . A memory cell of a dynamic random access memory, comprising: a write word line, a write bit line, a write transistor, a read word line, a read bit line and a read transistor, wherein the read transistor comprises a plurality of channel layers, and respective materials of the plurality of channel layers are different from each other;
 wherein a gate electrode of the write transistor is connected to the write word line, a first electrode of the write transistor is connected to the write bit line, a second electrode of the write transistor is connected to a gate electrode of the read transistor, the first electrode of the write transistor is one of a source electrode and a drain electrode of the write transistor, and the second electrode of the write transistor is the other of the source electrode and the drain electrode of the write transistor; and   wherein a first electrode of the read transistor is connected to the read bit line, a second electrode of the read transistor is connected to the read word line, the first electrode of the read transistor is one of a source electrode and a drain electrode of the read transistor, and the second electrode of the read transistor is the other of the source electrode and the drain electrode of the read transistor.   
     
     
         2 . The memory cell according to  claim 1 , wherein each of the plurality of channel layers is made of an amorphous indium zinc oxide material, an amorphous indium gallium zinc oxide material, an amorphous tungsten oxide material, or an amorphous indium tin oxide material. 
     
     
         3 . The memory cell according to  claim 1 , wherein the read transistor comprises the source electrode, the drain electrode, a bottom gate, a bottom gate insulating layer covering the bottom gate, and the plurality of channel layers stacked in sequence from bottom to top with the bottom gate insulating layer as a bottom layer, and each of the source electrode of the read transistor and the drain electrode of the read transistor is in contact with a topmost channel layer in the plurality of channel layers; and
 wherein the gate electrode of the read transistor comprises the bottom gate, and the second electrode of the write transistor is connected to the bottom gate of the read transistor.   
     
     
         4 . The memory cell according to  claim 2 , wherein the read transistor comprises the source electrode, the drain electrode, a bottom gate, a bottom gate insulating layer covering the bottom gate, and the plurality of channel layers stacked in sequence from bottom to top with the bottom gate insulating layer as a bottom layer, and each of the source electrode of the read transistor and the drain electrode of the read transistor is in contact with a topmost channel layer in the plurality of channel layers; and wherein the gate electrode of the read transistor comprises the bottom gate, and the second electrode of the write transistor is connected to the bottom gate of the read transistor. 
     
     
         5 . The memory cell according to  claim 1 , wherein the read transistor comprises the source electrode, the drain electrode, a bottom gate, a bottom gate insulating layer, the plurality of channel layers, a top gate insulating layer and a top gate, the bottom gate insulating layer covers the bottom gate, the plurality of channel layers are stacked in sequence from bottom to top with the bottom gate insulating layer as a bottom layer, and each of the source electrode of the read transistor and the drain electrode of the read transistor is in contact with a topmost channel layer in the plurality of channel layers;
 wherein the gate electrode of the read transistor comprises the top gate and the bottom gate, and the second electrode of the write transistor is connected to the bottom gate of the read transistor;   wherein the read transistor is covered with an insulating protection layer, and the insulating protection layer is provided with an opening exposing a portion of the top gate; and   wherein each of the source electrode of the read transistor and the drain electrode of the read transistor penetrates the insulating protection layer and is in contact with the topmost channel layer in the plurality of channel layers.   
     
     
         6 . The memory cell according to  claim 2 , wherein the read transistor comprises the source electrode, the drain electrode, a bottom gate, a bottom gate insulating layer, the plurality of channel layers, a top gate insulating layer and a top gate, the bottom gate insulating layer covers the bottom gate, the plurality of channel layers are stacked in sequence from bottom to top with the bottom gate insulating layer as a bottom layer, and each of the source electrode of the read transistor and the drain electrode of the read transistor is in contact with a topmost channel layer in the plurality of channel layers;
 wherein the gate electrode of the read transistor comprises the top gate and the bottom gate, and the second electrode of the write transistor is connected to the bottom gate of the read transistor;   wherein the read transistor is covered with an insulating protection layer, and the insulating protection layer is provided with an opening exposing a portion of the top gate; and wherein each of the source electrode of the read transistor and the drain electrode of the read transistor penetrates the insulating protection layer and is in contact with the topmost channel layer in the plurality of channel layers.   
     
     
         7 . The memory cell according to  claim 5 , wherein the insulating protection layer is made of aluminum oxide or silicon dioxide. 
     
     
         8 . The memory cell according to  claim 5 , wherein the read transistor further comprises a glass substrate layer, and the bottom gate is located on the glass substrate layer. 
     
     
         9 . The memory cell according to  claim 5 , wherein the top gate is made of molybdenum, the bottom gate is made of molybdenum, the source electrode is made of molybdenum, the drain electrode is made of molybdenum, the top gate insulating layer is made of silicon dioxide, and the bottom gate insulating layer is made of silicon dioxide. 
     
     
         10 . A storage array, comprising a plurality of memory cells of the dynamic random access memory according to  claim 1 . 
     
     
         11 . A memory, comprising the storage array according to  claim 10 . 
     
     
         12 . An electronic device, comprising the memory according to  claim 11 .