Systems and methods for flexible bank addressing in digital computing-in-memory (dcim)

Abstract

A method for flexible bank addressing in digital computing-in-memory (DCIM). The method includes providing bank groups, each of the bank groups comprising a respective number of memory banks, each memory bank configured to store a corresponding portion of input feature map data. The method includes reading, during a first clock cycle, a first portion of the input feature map data from a first one of the bank groups and a second portion of the input feature map data from a second one of the bank groups. The method includes performing a first multiply—accumulate operation using the first portion and the second portion. The method includes reading, during a second clock cycle, a third portion of the input feature map data from the first bank group. The method includes performing a second multiply—accumulate operation using the second portion and the third portion.

What is claimed is: 
     
         1 . A system, comprising:
 a plurality of bank groups, each of the plurality of bank groups comprising a respective number of memory banks that store respective input data; and   a memory controller to:
 read, during a first clock cycle, first input data from a first one of the plurality of bank groups, second input data from a second one of the plurality of bank groups, and third input data from a third one of the plurality of bank groups; 
 execute a first operation using the read first input data, the read second input data, and the read third input data; 
 read, during a second clock cycle, fourth input data from the first bank group; and 
 execute a second operation using the read second input data, the read third input data, and the read fourth input data. 
   
     
     
         2 . The system of  claim 1 , wherein the respective input data comprise input feature map data, and wherein each of the first and second operations comprises a respective multiply-accumulate operation. 
     
     
         3 . The system of  claim 1 , wherein the memory controller is to:
 read, during a third clock cycle, fifth input data from the second bank group; and   execute a third operation using the read third input data, the read fourth input data, and the read fifth input data.   
     
     
         4 . The system of  claim 1 , wherein the first input data, the second input data, the third input data, and the fourth input data form contiguous first, second, third, and fourth data rows, respectively. 
     
     
         5 . The system of  claim 1 , wherein the memory controller is to:
 during the first clock cycle, receive a first address, a second address, and a third address to read the first input data, the second input data, and the third input data, respectively.   
     
     
         6 . The system of  claim 5 , wherein the memory controller is to:
 during the second clock cycle, receive a fourth address to read the fourth input data.   
     
     
         7 . The system of  claim 6 , wherein the fourth address is updated from the first address to read the fourth input data, while the second address and the third address remain same. 
     
     
         8 . The system of  claim 1 , wherein during the second clock cycle when reading the fourth input data from the first bank group, the second input data and the third input data remain stored in respective registers coupled to the second bank group and the third bank group, respectively. 
     
     
         9 . The system of  claim 1 , wherein the memory controller is to:
 during the second clock cycle, write data for at least one memory bank of the first bank group.   
     
     
         10 . The system of  claim 1 , wherein the memory controller is to:
 write, during a third clock cycle, data for at least one memory bank of the first bank group; and   read, during the third clock cycle, fifth input data from the second bank group.   
     
     
         11 . A circuit, comprising:
 a plurality of bank groups, each of the plurality of bank groups comprising a respective number of memory banks that store respective input data; and   a memory controller to:
 read, during a first clock cycle, first input data from a first one of the plurality of bank groups and second input data from a second one of the plurality of bank groups; 
 perform a first operation using the read first input data and the read second input data; 
 read, during a second clock cycle, third input data from the first bank group; 
 write, during the second clock cycle, data for at least one memory bank of the first bank group along with reading the third input data; and 
 perform a second operation using the read second input data and the read third input data. 
   
     
     
         12 . The circuit of  claim 11 , wherein the respective input data comprise input feature map data, and wherein each of the first and second operations comprises a respective multiply-accumulate operation. 
     
     
         13 . The circuit of  claim 11 , wherein the first input data, the second input data, and the third input data form contiguous first, second, and third data rows, respectively. 
     
     
         14 . The circuit of  claim 11 , wherein the memory controller is to:
 during the first clock cycle, receive a first address and a second address to read the first input data and the second input data, respectively.   
     
     
         15 . The circuit of  claim 14 , wherein the memory controller is to:
 during the second clock cycle, receive a third address updated from the first address to read the third input data, while the second address remains same.   
     
     
         16 . The circuit of  claim 11 , wherein the memory controller is to:
 read, during a third clock cycle, fourth input data from the second bank group; and   write, during the third clock cycle, second data for at least one memory bank of the second bank group along with reading the fourth input data.   
     
     
         17 . The circuit of  claim 16 , wherein the first input data, the second input data, the third input data, and the fourth input data form contiguous first, second, third, and fourth data rows, respectively. 
     
     
         18 . A method, comprising:
 reading, during a first clock cycle, first input data from a first one of a plurality of bank groups and second input data from a second one of the plurality of bank groups, wherein each of the plurality of bank groups comprises a respective number of memory banks, each memory bank configured to store respective input data;   performing a first operation using the read first input data and the read second input data;   reading, during a second clock cycle, third input data from the first bank group;   performing a second operation using the read second input data and the read third input data;   writing, during a third clock cycle, data for at least one memory bank of the first bank group; and   reading, during the third clock cycle, fourth input data from the second bank group.   
     
     
         19 . The method of  claim 18 , further comprising:
 performing a third operation using the read third input data and the read fourth input data.   
     
     
         20 . The method of  claim 18 , further comprising:
 writing, during a fourth clock cycle, second data for at least one memory bank of the second bank group; and   reading, during the fourth clock cycle, fifth input data from the first bank group.