Semiconductor design system and method of designing a semiconductor device using the same

Abstract

A semiconductor design system and a method for designing a semiconductor device using the system include a design tool configured to: determine a target circuit block to designed; select a standard cell configured to perform a function of the target circuit block; determine a detailed configuration of the target circuit block according to a power characteristic and an input/output characteristic of the target circuit block; based on circuit block information including the detailed configuration of the target circuit block, a device type to which the target circuit block is applied, and an integration location for the target circuit block, select an alt-standard cell among a plurality of alt-standard cells associated with the selected standard cell, for which the alt-standard cell has circuit block information that most closely matches the circuit block information for the target circuit block; and lay out the target circuit block by loading the selected alt-standard cell.

What is claimed is: 
     
         1 . A semiconductor design system comprising:
 a design information medium configured to provide first design information and second design information, the first design information including information about a plurality of circuit blocks configured to be integrated into a semiconductor device and at least one function of the plurality of circuit blocks, and the second design information including an integration location of the plurality of circuit blocks and an input/output characteristic of the plurality of circuit blocks;   a cell library configured to a store layout pattern of each of the plurality of circuit blocks as a different one of a plurality of standard cells; and   a design tool operably coupled to the design information medium and the cell library, configured to select a standard cell, among the plurality of standard cells, including a layout pattern of a target circuit block based on the first design information and the second design information, and configured to load the layout pattern of the selected standard cell;   wherein each of the plurality of standard cells of the cell library is categorized based on the first design information; and   wherein each of the standard cells includes a plurality of alt-standard cells, each of the plurality of alt-standard cells having a different layout pattern based on the second design information.   
     
     
         2 . The semiconductor design system of  claim 1 , further comprising a layout data medium operably coupled to the design tool and configured to determine electrical characteristics of the target circuit block that is laid out and configured to store the determination results as layout data. 
     
     
         3 . The semiconductor design system of  claim 1 , wherein the design tool comprises:
 a control module configured to determine the target circuit block based on the first design information and configured to generate a control command that selects the alt-standard cell based on the second design information;   a simulation module configured to lay out the target circuit block in a form of the selected alt-standard cell in response to the control command;   a determination module configured to determine electrical characteristics of the target circuit block that is laid out; and   a correction module configured to correct at least one of a size and an integration location of the alt-standard cells based on the determination results of the determination module.   
     
     
         4 . The semiconductor design system of  claim 3 , further comprising a layout data medium configured to determine the electrical characteristics of the target circuit block that is laid out and configured to store results of the determination as layout data,
 wherein the design tool further comprises a comparison module configured to compare the electrical characteristics and structural characteristic of the target circuit block with reference layout data.   
     
     
         5 . The semiconductor design system of  claim 4 , wherein the layout data medium is configured to receive a corrected size of an electric component in the target circuit block corrected by the correction module and a corrected electrical characteristic of the target circuit block. 
     
     
         6 . The semiconductor design system of  claim 1 , wherein the standard cell comprises a circuit block configured to perform a first function of the at least one function,
 wherein the standard cell comprises:   a first alt-standard cell designed with an interval of a minimum feature size;   a second alt-standard cell including electric components in the circuit block arranged to extend longer in a first direction; and   a third alt-standard cell including electric components in the circuit block arranged to extend longer in the second direction than in the first direction, where the second direction is different from the first direction.   
     
     
         7 . The semiconductor design system of  claim 6 , wherein the second alt-standard cells and the third alt-standard cells comprise the same quantity of transistors. 
     
     
         8 . A method of designing a semiconductor device, the method comprising:
 determining, by a design tool, a target circuit block to designed;   identifying, by the design tool, a function of the target block;   selecting, by the design tool, a standard cell configured to perform the function of the target circuit block;   determining, by the design tool, a detailed configuration of the target circuit block according to a power characteristic and an input/output characteristic of the target circuit block;   based on circuit block information including the detailed configuration of the target circuit block, a device type to which the target circuit block is applied, and an integration location for the target circuit block, selecting, by the design tool, an alt-standard cell among a plurality of alt-standard cells associated with the selected standard cell, for which the alt-standard cell has circuit block information that most closely matches the circuit block information for the target circuit block; and   laying out, by the design tool, the target circuit block by loading the selected alt-standard cell.   
     
     
         9 . The method of  claim 8 , further comprising determining electrical characteristics of the laid out target circuit block. 
     
     
         10 . The method of  claim 8 , wherein a size of electric components in the selected alt-standard cell is corrected when a difference between electrical characteristics of the laid out target circuit block and reference electrical characteristics of the target circuit block is beyond a margin of error. 
     
     
         11 . The method of  claim 10 , wherein the electric components comprise a plurality of transistors, a plurality of wirings configured to connect the transistors, and a plurality of contacts configured to connect the transistors with the wirings, and
 wherein correcting sizes of the electric components comprises changing at least one of an active area of the transistor, a gate width of the transistor, the width and length of the wiring, and a size of a contact configured to electrically connect the wirings to each other.   
     
     
         12 . A semiconductor design system comprising:
 a processor; and   memory including stored instructions that, when executed by the processor, perform functions of a design tool including:   generating design information and a control command that selects detailed configurations based on the design information for a target circuit block that performs a function;   in response to receiving the command, selecting a standard cell, from a plurality of standard cells, that performs the function;   selecting an alt-standard cell included in the standard cell, which alt-standard cell has detailed design information that most closely matches design information for the target circuit block; and   laying out the target circuit block by loading the selected alt-standard cell.