Semiconductor devices

Abstract

A semiconductor device includes a substrate insulating layer, a gate structure extending in a first direction on the substrate insulating layer, a plurality of channel layers spaced apart from each other in a second direction, the second direction perpendicular to an upper surface of the substrate insulating layer, the plurality of channel layers on the substrate insulating layer and surrounded by the gate structure, a first source/drain region and a second source/drain region, on both sides of the gate structure and connecting to the plurality of channel layers, a first spacer layer below the first source/drain region, and a second spacer layer below the second source/drain region, and a backside contact plug partially recessing a lower surface of the first source/drain region through the substrate insulating layer and the first spacer layer.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate insulating layer;   a gate structure extending in a first direction on the substrate insulating layer;   a plurality of channel layers spaced apart from each other in a second direction, the second direction perpendicular to an upper surface of the substrate insulating layer;   the plurality of channel layers on the substrate insulating layer and surrounded by the gate structure;   a first source/drain region and a second source/drain region, on both sides of the gate structure and connecting to the plurality of channel layers;   a first spacer layer below the first source/drain region, and a second spacer layer below the second source/drain region; and   a backside contact plug partially recessing a lower surface of the first source/drain region through the substrate insulating layer and the first spacer layer,   wherein each of the first and second source/drain regions includes
 a first epitaxial layer covering side surfaces of the plurality of channel layers, and 
 a second epitaxial layer on the first epitaxial layer, 
   the first source/drain region includes
 a backside epitaxial layer covering an upper portion of the backside contact plug, and 
 a concentration of a non-silicon element included in the backside epitaxial layer is greater than a concentration of a non-silicon element included in the second epitaxial layer. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the non-silicon element is at least one of germanium (Ge), boron (B), gallium (Ga), indium (In), phosphorus (P), arsenic (As), or antimony (Sb). 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first and second spacer layers comprise materials, different from materials of the first and second epitaxial layers. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the first and second spacer layers comprise at least one of SiN, SiO, SiCN, SiOC, or SiOCN. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the backside epitaxial layer is between the second epitaxial layer and the backside contact plug. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the first and second epitaxial layers of the first source/drain region are spaced apart from the backside contact plug. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the plurality of channel layers comprise a lowermost channel layer in a lowermost portion, and
 wherein upper ends of the first and second spacer layers are on a level lower than a lower surface of the lowermost channel layer.   
     
     
         8 . The semiconductor device of  claim 1 , wherein
 the gate structure comprises
 a gate electrode surrounding the plurality of channel layers, 
 gate dielectric layers between the gate electrode and the plurality of channel layers, and 
 gate dielectric layers further between the gate electrode and the substrate insulating layer, 
   wherein upper ends of the first and second spacer layers are on a level, higher than a lower surface of the gate electrode.   
     
     
         9 . The semiconductor device of  claim 1 , further comprising a front side contact plug partially recessing an upper surface of the second source/drain region. 
     
     
         10 . The semiconductor device of  claim 1 , wherein
 a lower end of the first epitaxial layer of the first source/drain region is in contact with the first spacer layer, and   a lower end of the first epitaxial layer of the second source/drain region is in contact with the second spacer layer.   
     
     
         11 . The semiconductor device of  claim 1 , wherein the first and second source/drain regions are spaced apart from the substrate insulating layer. 
     
     
         12 . The semiconductor device of  claim 1 , further comprising a void on the second spacer layer in the second source/drain region. 
     
     
         13 . A semiconductor device comprising:
 a gate structure extending in one direction;   a source/drain region on a side of the gate structure;   a backside contact plug connecting to the source/drain region from below the source/drain region; and   a spacer layer surrounding at least a portion of the backside contact plug below the source/drain region,   wherein the source/drain region includes
 a first epitaxial layer contacting the gate structure, 
 a second epitaxial layer on the first epitaxial layer, and 
 a backside epitaxial layer between the second epitaxial layer and the backside contact plug, 
   wherein
 the first epitaxial layer includes a non-silicon element having a first concentration, 
 the second epitaxial layer includes a non-silicon element having a second concentration, the second concentration greater than the first concentration, and 
 the backside epitaxial layer includes a non-silicon element having a third concentration, the third concentration greater than the second concentration. 
   
     
     
         14 . The semiconductor device of  claim 13 , wherein the first and second epitaxial layers are spaced apart from the backside contact plug. 
     
     
         15 . The semiconductor device of  claim 14 , wherein the spacer layer comprises at least one of silicon oxide, silicon nitride, or silicon oxynitride. 
     
     
         16 . The semiconductor device of  claim 13 , wherein
 the source/drain region further comprises an intermediate epitaxial layer between the first epitaxial layer and the second epitaxial layer, and   the intermediate epitaxial layer includes a non-silicon element having a fourth concentration, the fourth concentration greater than the first concentration and less than the second concentration.   
     
     
         17 . The semiconductor device of  claim 13 , wherein
 the first epitaxial layer covers the spacer layer and surrounds at least a portion of the backside contact plug, and   the second epitaxial layer is spaced apart from the spacer layer.   
     
     
         18 . The semiconductor device of  claim 17 , wherein the spacer layer comprises at least one of silicon (Si) or germanium (Ge). 
     
     
         19 . A semiconductor device comprising:
 a substrate insulating layer;   a gate structure extending in a first direction on the substrate insulating layer;   a plurality of channel layers spaced apart from each other in a second direction, the second direction perpendicular to an upper surface of the substrate insulating layer;   the plurality of channel layers on the substrate insulating layer, and surrounded by the gate structure;   a first source/drain region on a first side of the gate structure and connecting to the plurality of channel layers;   a second source/drain region on a second side of the gate structure, the second side opposite to the first side and connecting to the plurality of channel layers;   a first spacer layer between the first source/drain region and the substrate insulating layer;   a second spacer layer between the second source/drain region and the substrate insulating layer;   a backside contact plug penetrating the substrate insulating layer and the first spacer layer and connecting to the first source/drain region; and   a front side contact plug partially recessing the upper surface of the second source/drain region,   wherein the first source/drain region includes
 a backside epitaxial layer contacting the backside contact plug, and 
 a concentration of a non-silicon element included in the backside epitaxial layer is greater than a concentration of a non-silicon element included in the second source/drain region. 
   
     
     
         20 . The semiconductor device of  claim 19 , further comprising a backside power structure connecting to the backside contact plug below the substrate insulating layer.