Contact Formation Method and Related Structure

Abstract

A method and structure for forming semiconductor device includes forming an opening in a dielectric layer to expose a source/drain region. In some embodiments, the method further includes depositing a first metal layer in the opening and over the source/drain region. Thereafter, in some examples, the method further includes performing an annealing process to modulate a grain size of the first metal layer. In various embodiments, the method further includes depositing a second metal layer over the annealed first metal layer. In some embodiments, the second metal layer has a substantially uniform phase.

What is claimed is: 
     
         1 . A method, comprising:  
       forming an opening along a backside surface of a substrate to expose a substrate region; 
       depositing a first metal layer in the opening along the backside surface and contacting the substrate region; 
       annealing the first metal layer to increase a grain size of the first metal layer; and 
       depositing a second metal layer over the annealed first metal layer in the opening along the backside surface, wherein the second metal layer has a substantially uniform phase. 
     
     
         2 . The method of  claim 1 , wherein the substrate region includes a source/drain region or a body contact region. 
     
     
         3 . The method of  claim 1 , wherein the first metal layer defines a contact plug, and wherein the second metal layer defines a via. 
     
     
         4 . The method of  claim 1 , wherein the first metal layer and the second metal layer collectively define a backside contact structure. 
     
     
         5 . The method of  claim 4 , wherein the backside contact structure provides contact to a backside power delivery network. 
     
     
         6 . The method of  claim 1 , wherein the first metal layer includes cobalt (Co), and wherein the second metal layer include tungsten (W). 
     
     
         7 . The method of  claim 1 , wherein the annealed first metal layer has a grain size in a range between about 30-90. nm 2 . 
     
     
         8 . The method of  claim 1 , wherein the second metal layer includes alpha-tungsten (α-W).  
     
     
         9 . The method of  claim 1 , wherein the annealing is performed at a temperature of between about 250-400 degrees Celsius, in a 30-70 % H2 ambient environment, at a pressure of between about 10-30 Torr, and for a duration of between about 5-10 minutes. 
     
     
         10 . The method of  claim 1 , wherein greater than 50% of the annealed first metal layer has a hexagonal close-packed (HCP) crystal structure. 
     
     
         11 . The method of  claim 1 , wherein a ratio of a first portion of the annealed first metal layer that has a hexagonal close-packed (HCP) crystal structure to a second portion of the annealed first metal layer that has a face-centered cubic (FCC) crystal structure is in a range between about 1-2. 
     
     
         12 . A method, comprising:  
       forming a first contact plug in contact with a top side of a substrate region along a frontside surface of a substrate and a second contact plug in contact with a bottom side of the substrate region along a backside surface of the substrate; 
       modulating a grain size of a first metal layer used to form each of the first and second contact plugs; and 
       after modulating the grain size of the first metal layer, forming a first via over the first contact plug along the frontside surface of the substrate and a second via over the second contact plug along the backside surface of the substrate; 
       wherein a phase of a second metal layer used to form each of the first and second vias includes an alpha phase. 
     
     
         13 . The method of  claim 12 , wherein the substrate region includes a source/drain region or a body contact region. 
     
     
         14 . The method of  claim 12 , wherein the second contact plug and the second via provide contact to a backside power delivery network. 
     
     
         15 . The method of  claim 12 , wherein the modulating the grain size of the first metal layer includes annealing the first metal layer. 
     
     
         16 . The method of  claim 12 , further comprising prior to forming the first and second contact plugs, forming a silicide layer over at least one of the top side of the substrate region and the bottom side of the substrate region, and forming the first and second contact plugs over the silicide layer. 
     
     
         17 . The method of  claim 12 , wherein the first metal layer includes cobalt (Co), and wherein the second metal layer include tungsten (W). 
     
     
         18 . The method of  claim 12 , wherein after modulating the grain size of the first metal layer, the grain size of the first metal layer is in a range between about 30-90 nm 2 . 
     
     
         19 . A semiconductor device, comprising: 
 a substrate;   a contact plug portion of a backside contact structure, the contact plug portion formed along a backside surface of the substrate and contacting a substrate region, wherein the substrate region includes a source/drain region or a body contact region, wherein the contact plug portion includes a cobalt (Co) layer, and wherein a majority of the Co layer has a hexagonal close-packed (HCP) crystal structure; and   a via portion of the backside contact structure, the via portion formed over the contact plug portion along the backside surface of the substrate, wherein the via portion includes a tungsten (W) layer formed in an alpha phase.   
     
     
         20 . The semiconductor device of  claim 19 , wherein the contact plug portion and the via portion of the backside contact structure provide contact to a backside power delivery network.