Overlay metallization field effect transistor

Abstract

A high-frequency, high-power FET constructed upon a planar substrate with a repeated pattern of gate, source, and drain connections wherein any two are connected with metallization layers adjacent to and separated from the semiconductor substrate. The third element is interconnected with an overlay metallization layer separated from the lower two metallization layers by an insulating dielectric. The overlay layer is preferably grounded for minimum feedback capacitance.

It is claimed that: 
     
       1. The method comprising the steps of: providing a substrate of semiconductor material;   growing an epitaxial layer on said substrate;   covering said epitaxial layer with a first insulating layer;   removing portions of said first insulating layer from said epitaxial layer in first and second predetermined patterns;   depositing first and second metal layers in said first and second predetermined patterns;   covering said first and second metal layers and said first insulating layers with a second insulating layer;   removing portions of said second insulating layer and said first insulating layer from regions interspersed between portions of said first and second metal layers;   depositing a third metal layer upon said epitaxial layer in said interspersed regions; to form Schottky barrier contacts   removing the remaining portions of said first and second insulating layers;   covering portions of said first, second, and third metal layers with a third insulating layer;   removing portions of said third insulating layer above a predetermined one of said first, second and third metal layers; and   depositing a fourth metal layer, said fourth metal layer being patterned to interconnect portions of said predetermined one of said first, second, and third metal layers.   
     
     
       2. The method of claim 1 wherein at least two of said first, second, and third metal layers comprise an alloy of gold and germanium. 
     
     
       3. The method of claim 2 wherein said first, second, and third insulating layers comprise silicon dioxide. 
     
     
       4. The method of claim 3 wherein said depositing said fourth metal layer comprises the steps of: depositing a layer of titanium; and   depositing a layer of gold.