Discretionary fly wire chip interconnection

Abstract

A module for LSI chips includes an orthogonal array of sets of pads and fan-out metallization for a large number of chips. Running parallel to the sides of the chips and the fan-out area are several parallel prefabricated, thin film engineering change interconnection lines terminating in pads adjacent to the fan-out. The pads are arranged to permit discretionary connections of the fan-out pads to the engineering change pads with minimal crossovers by means of short fly wires. A staggered pad arrangement minimizes potential crossovers and maximizes the number of interconnection lines that can be fabricated.

Having thus described my invention, what I claim as new and desire to secure by letters patent is: 
     
       1. A module for an array of integrated circuit chips said module having an upper surface with a set of pads for connection thereto and a fan-out area with fan-out pads surrounding said chips and metallization beneath the surface providing standard connections between pads connected to said chips, said chips being arranged upon said module in a substantially orthogonal pattern upon said upper surface with engineering change metallization deposited upon said upper surface adjacent to said fan-out areas, the improvement comprising a plurality of generally either parallel or orthogonal engineering change lines adjacent to and between said chips and said fan-out pads upon said upper surface, said engineering change lines being arranged heirarchically with higher level and lower level lines, said higher level lines having the greater lengths and said lower level lines having the shorter lengths with successive levels of lines in said heirarchy generally being oriented orthogonally with respect to each other, with terminal pads located at one of the ends of said lower level lines and pads located upon said higher level lines adjacent to a juxtaposed terminal pad upon a lower level line with a fly wire connected between said juxtaposed pads and a fly wire bonded between a fan-out pad and another pad upon said lower level line for providing a connected between said fan-out pad and said higher level engineering change line, whereby engineering change connections are constructed upon the upper surface of a module with fly wire connections which are extremely short in order to minimize the space, bulk, resistance, and inductance of the fly wire connection and permit such engineering change interconnections to be made between different chips. 
     
     
       2. A module for an array of integrated circuit chips said module having an upper surface with a set of pads for connection thereto and a fan-out area with fan-out pads surrounding said chips and having metallization beneath said surface providing standard connections between pads connected to said chips, said chips being arranged upon said module in an orthogonal pattern, with engineering change metallization deposited upon said upper surface of said substrate adjacent to said fan-out areas, the improvement comprising providing in said metallization respectively a plurality of orthogonal and parallel engineering change lines adjacent to and between said chips and fan-out pads, said lines being hierarchically organized with the lowest nth order lines aligned substantially orthogonally to the next higher, n+1 order lines and terminating adjacent thereto in nth order terminal pads, where n is an integer greater than one, said nth order lines terminating in pads adjacent to said chips at one end and in said nth order terminal pads at the other end thereof, said n+1th order lines including corresponding pads juxtaposed immediately adjacent to said terminal pads, and a plurality of fly wires bonded to said fanout pads and said engineering change line pads and between said engineering change line terminal pads and said corresponding pads. 
     
     
       3. A module in accordance with claim 1 or 2 wherein said engineering change lines are arranged oriented in a plurality of directions with engineering change pads at the ends thereof and adjacent to the pads of other lines juxtaposed therewith. 
     
     
       4. A module in accordance with claim 1 or 2 wherein said engineering change lines bend to extend within the space between two adjacent chips with pads adjacent to the fan-out pads on the periphery of said chips. 
     
     
       5. A module in accordance with claim 1 or 2 wherein a gap between a pair of said lower level lines separated from each other by a said higher level engineering change line is bridged by means of a said fly wire. 
     
     
       6. A module in accordance with claim 1 or 2 wherein said engineering change lines are segmented and with the segmented ends thereof staggered with pads on the segmented ends thereof, whereby said staggered pads are juxtaposed in a diagonal arrangement whereby said segmented lines can be joined on a lengthwise basis or a chip joining basis or both as required. 
     
     
       7. A module in accordance with claim 1 or 2 wherein beneath the surface of said module electrical circuit wiring is provided connecting the chip pads together by means of vias and the direction of said circuit wiring is at an angle near 45° with respect to said engineering change wiring whereby electrical coupling is minimized. 
     
     
       8. A module for an array of integrated circuit chips having an upper surface with a set of pads for connection thereto and a fan-out area with fan-out pads surrounding said chips arranged upon said module in a substantially orthogonal pattern upon said upper surface and metallization beneath said upper surface for providing standard connections between pads connected to said chips, with engineering change metallization deposited upon said upper surface adjacent to said fan-out areas, the improvement comprising a plurality of parallel engineering change lines adjacent to and between said chips and said fan-out pads upon said upper surface, with said engineering change lines bending to extend within the space between two adjacent chips and including juxtaposed pads adjacent to said fan-out pads with fly wires connected between said fan-out pads and said juxtaposed pads on said engineering change lines. 
     
     
       9. A module for an array of integrated circuit chips having an upper surface with a set of pads for connection thereto and a fan-out area with fan-out pads surrounding said chips arranged upon said module in a substantially orthogonal pattern upon said upper surface and metallization beneath said upper surface for providing standard connections between pads connected to said chips, with engineering change metallization deposited upon said upper surface adjacent to and between said chips and said fan-out areas, the improvement comprising a plurality of engineering change lines adjacent to said fan-out areas upon said upper surface with said lines being segmented and with the segmented ends thereof being staggered in position with staggered pads on the segmented ends of said segmented ends of said lines, whereby said staggered pads are juxtaposed in a diagonal alignment and said staggered pads are adjacent to said fan-out pads and said staggered lines can be joined on a lengthwise basis by connecting corresponding staggered pads together.