Method of manufacturing an integrated circuit device having vertical field effect transistors

Abstract

A method of manufacturing an integrated circuit device including vertical static induction transistors (SIT) having a first recess between the gate region and the drain (or source) region to reduce the capacitance between both regions and a second recess on an outer surface of the SIT gate to reduce the gate capacitance and a minority carrier storage. The method includes the steps of removing a masking film on the SIT channel region while leaving the masking film at the portions of the gate region and the drain region; forming the first and the second recesses in the channel region; locally oxidizing the exposed channel region; and forming the gate region and the drain region by removing the masking film.

What is claimed is: 
     
       1. A method of manufacturing an integrated circuit device including at least one vertical field effect transistor, comprising the steps of: forming a first single crystal semiconductor layer of one conductivity type and of a low impurity density on a second single crystal semiconductor layer of one conductivity type and of a high impurity density;   depositing a masking film including a nitride over a whole surface of said first layer;   removing selected portions of said masking film while leaving at least first and second portions thereof intact where said second portion circumscribes said first portion;   forming a first recess between said first and second portions of the masking film and a second recess at least partially outside of said second portion of the masking film in said first layer by use of said masking film at least as a mask for etching said first layer;   selectively oxidizing the exposed surface of said first layer by use of the intact masking film;   forming a second single crystal region of opposite conductivity type to said one conductivity type in said first layer through the window opened by removing an insulator film of said second portion of the masking film; and   forming a first single crystal region of one conductivity type and of a high impurity density in said first layer through the window opened by removing an insulator film of said first portion of the masking film;   whereby a transistor is formed by using said first layer, said second layer, said first region and said second region as the channel region, source region, drain region and the gate region, respectively, of the transistor.   
     
     
       2. A method of manufacturing an integrated circuit device including at least one vertical field effect transistor as claimed in claim 1; wherein said masking film is at least composed of a nitride film, and a polycrystal film of high resistivity under said nitride film on said first layer; and selectively oxidizing the exposed side edges of said polycrystal film of said first and second portions and the exposed surface of said first layer and then removing the oxide film on the surface of said first layer before carrying out the steps of forming the first and second recesses. 
     
     
       3. A method of manufacturing an integrated circuit device including at least one vertical field effect transistor as claimed in claim 1; wherein said first layer has a surface of a [100] crystallographic plane, and said first and second recesses are formed at the same time by an anisotropic etching technique which has an etching speed at least as fast as a [111] crystallographic plane as compared with other crystallographic planes. 
     
     
       4. A method of manufacturing an integrated circuit device including at least one vertical field effect transistor as claimed in claim 3; wherein said first recess is formed shallower than said second recess by forming the surface width of said first layer between said first and second portions of the masking film smaller than that between said second portion and other portions of the masking film, and said first region is formed shallower than said first recess and said second region is formed deeper than said first recess. 
     
     
       5. A method of manufacturing an integrated circuit device including at least one vertical field effect transistor as claimed in claim 1; comprising the steps of: forming said first layer on said second layer;   depositing said masking film on said first layer;   removing selected portions of said masking film while leaving at least said first and second portions and a third portion thereof intact where said third portion is formed spaced from the outside of said second region;   forming said first and second recesses and a third recess between said second and third portions of the masking film in said first layer;   selectively oxidizing the exposed surface of said first layer by use of said intact masking film;   forming said second region and a third region of said opposite conductivity in said first layer thorugh the windows opened by removing an insulator film of said second and third portions of the masking film; and   forming said first region;   whereby said transistor and a lateral transistor are formed, the latter of which is composed of said third region as an emitter or an injector, said first layer as a base, said second layer as a base electrode region and said second region as a collector.   
     
     
       6. A method of manufacturing an integrated circuit device including at least one vertical field effect transistor as claimed in claim 5; wherein a fourth portion of said masking film is left when leaving said first, second and third portions of masking film, the fourth portion being localized between said second and third portions, and said third recess being formed in said first layer between said second and fourth portions of the masking film and a fourth recess being formed between said third and fourth portions of the masking film in said first layer.