Fabrication method for controlled via hole process

Abstract

A method for forming via holes having a rounded sidewall profile includes exposing a layer or organic positive photoresist to a formic gas plasma while the surface of the photoresist layer is bombarded with ions and electrons in a high voltage biased environment in which the photoresist layer is capacitively coupled. The photoresist layer may be exposed to UV light either before or after the formic gas plasma step.

I claim: 
     
       1. A method for forming via holes having a rounded sidewall profile comprising the steps of: providing a layer of organic positive photoresist on the insulation layer,   exposing said photoresist layer to a formic gas plasma,   bombarding the surface of said photoresist layer with ions and electrons in a high voltage biased environment in which said photoresist layer is capacitively coupled whereby the solubility of the upper portion of said photoresist layer in a developer solution is increased,   imagewise exposing said photoresist layer to UV light, and   developing said photoresist layer.   
     
     
       2. A method as described in claim 1 whereby the step of imagewise exposing said photoresist layer to UV light is carried out before the formic gas plasma step. 
     
     
       3. A method as described in claim 1 whereby said organic positive photoresist is of the AZ-type. 
     
     
       4. A method as described in claim 1 whereby said photoresist layer is exposed for 10 to 60 seconds to the ion and electron bombardment. 
     
     
       5. A method as described in claim 1 whereby said photoresist layer is exposed for 15 to 25 seconds to the ion and electron bombardment. 
     
     
       6. A method as described in claim 1 whereby the voltage is 50 to 2000 volts. 
     
     
       7. A method as described in claim 1 whereby the voltage is 300 to 400 volts.