CMOS process

Abstract

A process is disclosed for fabricating complementary insulated gate field effect transistors including doped field isolation regions and optional punch through protection. In one embodiment of invention, a silicon substrate is provided which has N-type and P-type surface regions. First and second masks are formed overlying active areas of the two surface regions. A third mask is then formed overlying the first region and the first mask. P-type impurities are implanted into the second region with an implant energy which is sufficient to penetrate through the second mask but insufficient to penetrate through the third mask. A second P-type implant is performed with an implant energy insufficient to penetrate through either mask. The first implant will aid in preventing punch through while the second implant dopes the field region. A fourth mask is then formed overlying the second region and the second mask. A first N-type implant is performed at energy sufficient to penetrate through the first mask but insufficient to penetrate through the fourth mask. This implant provides punch through protection for P channel transistors to be formed later. A second N-type impurity is implanted into the surface at an implant energy insufficient to penetrate through the first mask to provided field doping. The silicon substrate is then oxidized to form a field oxide at portions of the first and second surface regions which are not covered by the first and second masks.

We claim: 
     
       1. A process for fabricating complementary insulated gate field effect transistors including doped field isolation regions which comprises the steps of: providing a silicon substrate having an N-type first surface region and a P-type second surface region;   forming first and second masks overlying active areas of said first and second surface;   forming a third mask overlying said first region and said first mask;   implanting first P-type impurities into said second region with an implant energy sufficient to penetrate through said second mask but insufficient to penetrate through said third mask;   implanting second P-type impurities into said second region with an implant energy insufficient to penetrate through said second mask;   forming a fourth mask overlying said second region and said second mask;   implanting first N-type impurities into said first region with an implant energy sufficient to penetrate through said first mask but insufficient to penetrate through said fourth mask;   implanting second N-type impurities into said first region with an implant energy insufficient to penetrate through said first mask;   and oxidizing to form a field oxide at portions of said first and second surface regions not overlaid by said first and second masks.   
     
     
       2. A process for fabricating complementary insulated gate field effect transistors including doped field isolation regions which comprises the steps of: providing a silicon substrate having an N-type first surface region and a P-type second surface region;   forming a first masking layer overlying said first and second surface regions;   patterning said first masking layer to leave portions overlying an active region of each of said first and second surface regions;   implanting P-type impurities into portions of said first and second regions not protected by said first masking layer;   forming a second masking layer overlying said second surface region;   implanting first N-type impurities into said first surface region at an implant energy sufficient for said first N-type impurities to penetrate through said first masking layer;   implanting second N-type impurities into said first surface not protected by said first masking layer;   and oxidizing to form a field oxide at portions of said first and second surface regions not overlaid by said first masking layer.   
     
     
       3. A process for fabricating complementary insulated gate field effect transistors including doped field isolation regions comprising the steps of: providing a silicon substrate having an N-type first surface region and a P-type second surface region;   providing a patterned first masking layer overlying selected areas of each of said first and second surface regions, respectively;   implanting P-type impurities into portions of said first and second surface region not masked by said first masking layer;   forming a second masking layer overlying said second surface region;   etching portions of said first surface region not protected by said first or second masks;   implanting N-type impurities into said first surface region using said first and second masking layers as implant masks;   and thermally oxidizing to form a field oxide at portions said first and second surface regions.   
     
     
       4. The process of claim 3 further comprising the step of implanting second P-type impurities into said second surface regions at an implant energy sufficient for said impurities to penetrate through said first masking layer but insufficient to penetrate through said second masking layer. 
     
     
       5. A process comprising the steps of: providing a silicon substrate having a surface, said surface having a first region of N-type conductivity and a second region of P-type conductivity;   forming a first masking layer selectively overlying said first and second regions;   implanting P-type impurity ions into said surface using said first masking layer as an implant mask;   forming a second masking layer overlying said second region;   etching said surface using said first and second masks as an etch mask;   implanting first N-type impurity ions into said surface using said first and second masking layers as an implant mask;   implanting second N-type impurity ions into said surface using said second masking layer as an implant mask;   and selectively oxidizing said surface to form a field oxide.   
     
     
       6. A process for fabricating complementary insulated gate field effect transistors comprising the steps of: providing a silicon substrate having a first region having a surface of first conductivity type and a second region having a surface of second conductivity type;   forming a first masking layer overlying said substrate;   forming a second patterned masking layer overlying said first masking layer and including masks over portions of each of said first and second regions;   implanting impurities of said second conductivity type into said substrate using said masks as ion implantation masks;   patterning said first masking layer using said masks as etch masks;   forming a third patterned masking layer overlying said second region;   implanting first and second impurities of first conductivity type, said first impurities implanted at an implant energy sufficient for said first impurities to penetrate said masking layer but not said third masking layer and said second impurities implanted at an implant energy such that said second impurities are masked by said first and third masking layers;   and oxidizing said substrate to form a field oxide.   
     
     
       7. A process for fabricating complementary insulated gate field effect transistors comprising the steps of: providing a silicon substrate having a first conductivity type and a second region with a surface of second conductivity type, each of said first and second regions including active portion and field portions;   forming a first masking layer overlying said substrate;   selectively implanting ions of first conductivity type into said field portions of said first and second regions;   selectively etching said field portion of said second region to remove substantially all of said ions of first conductivity type implanted therein;   selectively implanting ions of second conductivity type into said field portion of said second region using said first masking layer as an implantation mask;   and oxidizing said substrate to form a field oxide.   
     
     
       8. The process of claim 7 further comprising the steps of: forming a patterned layer of photoresist overlying said first masking layer;   using said photoresist as an implantation mask for said step of implanting ions of first conductivity type;   and etching said first masking layer using said photoresist as an etch mask.   
     
     
       9. The process of claim 7 further comprising the steps of: forming a patterned layer of photoresist overlying said first masking layer;   etching said first masking layer;   and using said photoresist and first masking layer as an implantation mask for said step of implanting ions of first conductivity type.   
     
     
       10. The process of claim 7 further comprising the step of selectively implanting second ions of second conductivity type through said first masking layer and into said active portion of said second region.