Control means for an integrated memory matrix display and its control process

Abstract

A control system for an integrated memory matrix display and its associated process is disclosed. The control system for the matrix display utilizes a first group of n row conductors and a second group of m column conductors which carry appropriate signals for excitation of an electro-optical display material at image points which form the integrated memory of a display. A first selection circuit is connected to n' address rows and to n row conductors where n is ≦2 n' and m read-write circuits, each connected to a column conductor and combine into k packages wherein each package has a maximum of l read-write circuits with the integers m, l and k being such that l is >1 and <m and k is >1 and <m. Each pth read-write circuit of package is connected to the pth row of a bidirectional data bus 21 with l rows, with the p being an integer such that p≧1 and ≦l. Also contained in this system is k processing circuits which are each connected on the one hand to a package of read-write circuits and on the other two a second selection circuit which itself is connected to k' address rows with k being ≦2 k' .

We claim: 
     
       1. Control means for a matrix display (9) having nxm image points arranged in matrix manner, a first group of n row conductors (L i ) and a second group of m column conductors (C j ) carrying appropriate signals for exciting an electrooptical display material, each image point (I ij ) of the display, formed from a capacitor whose dielectric is constituted by the display material, being associated with a row conductor (L i ), a column conductor (C j ) and a switch (5), each image point forming a memory point of the display in which it is possible to write, read and refresh an information, characterized in that the control means comprises m read-write circuits (15), each connected to a column conductor (C j ) for reading, writing and refreshing an information at the image points associated with said column conductor (C j ), said read-write circuits (15) being combined into k packages, each of which has at the most l read-write circuits, with m, l and k integers such that 1<l<m and l<k<m, the packages of read-write circuits being connected to a bidirectional data bus (21) of l rows, the pth read-write circuits (15) of each package being connected to the pth row of said bus, with p beig an integer such that 1≦p≦l, the reading, writing and refreshing operations performed by the read-write circuits being selected on the basis of control signals (20). 
     
     
       2. Control means according to claim 1, characterized in that it comprises processing means having k processing circuits (17), each connected to a package of read-write circuits (15), the reading, writing and refreshing operations performed by the read-write circuits being selected by means of processing circuits receiving the control signals (20) and supplying selection signals (35, E, R, L, 37) to the read-write circuits. 
     
     
       3. Control means according to claim 1, characterized in that it comprises a first selection circuit (13) connected at the input to n' address rows (14) and at the output to n row conductors (L i ) with n≦2 n'  for selecting a single row conductor at once. 
     
     
       4. Control means according to claim 2, characterized in that it comprises a second selection circuit (19) connected at the input to k' address rows (18) and at the output to k processing circuits (17), with k≦2 k'  for selecting a single package of column conductors (C j ) by choosing a single processing circuit (17) at once. 
     
     
       5. Control means according to claim 1, characterized in that each read-write circuit (15) comprises writing means (25, 27) which, in the information transfer direction, have a first processing circuit (250 and a first amplifier (27) which are interconnected, as well as reading means (29, 31, 33) connected in parallel to the writing means, said reading means having in the information transfer direction a second amplifier (29) connected both to a storage means (31) and to a second processing circuit (33), the storage means also being connected to the first processing circuit (25) to permit the refreshing of the information read and stored, the first processing circuit transmitting an information from the data bus or storage means to the first amplifier and the second processing circuit transmitting an information from the second amplifier to the data bus. 
     
     
       6. Control means according to claim 5, characterized in that the first processing circuit (25) comprises a first transistor (24) connected to the first amplifier (27) and used for transferring an information to be written to said first amplifier and a second transistor (26) connected on the one hand to the first transistor (24) and the first amplifier (27) and on the other hand to the storage means (31), said second transistor (26) transferring a read information to be refreshed to said first amplifier. 
     
     
       7. Control means according to claim 5, characterized in that the storage means (31) comprises a transistor (30) and a capacitor (32) which are interconnected, said transistor also being connected to the second processing circuit (33) and a second amplifier (29), whilst capacitor (32) is also connected to the first processing circuit (25). 
     
     
       8. Control means according to claim 5, characterized in that one of the first and second amplifiers (27, 29) is an inverting amplifier for applying an alternative signal to the image points. 
     
     
       9. A control means of a matrix display (9) having n·m image points arranged in matrix manner, a first group of n row conductors (L i ) and a second group of m column conductors (C j ) carrying appropriate signals for exciting an electrooptical display material, each image point (I ij ) of the display formed by a capacitor, whose dielectric is constituted by the display material being associated with a row conductor (L i ), a column conductor (C j ) and a switch (5), each image point constituting a memory point of the display in which it is possible to write, read and refresh an information characterized in that the control means comprises m read-write circuits (15), each connected to a column conductor (C j ) for writing, reading and refreshing an information at the image points associated with said column conductor (C j ), the read-write circuits (15) being connected to a bidirectional data bus (21), the reading, writing and refreshing operations performed by said read-write circuits (15) being selected on the basis of control signals (20), each read-write circuit comprising writing means (25, 27) which, in the information transfer direction, have a first processing circuit (25) and a first amplifier (27) which are connected together, as well as reading means (29, 31, 33) connected in parallel to the writing means, said reading means having in the information transfer direction, a second amplifier (29) connected both to the storage means (31) and to a second processing circuit (33), the storage means also being connected to the first processing circuit (25) to enable the read and stored information to be refreshed, the first processing circuit transmitting information from the data bus or storage means to the first amplifier and the second processing circuit transmitting an information from the second amplifier to the data bus. 
     
     
       10. Control means according to claim 9, characterized in that it comprises processing means (17) connected to read-write circuits (15), the reading, writing and refreshing operations performed by the read-write circuits being selected by a processing means receiving control signals and supplying selection signals (35, E, R, L, 37) to the read-write circuits. 
     
     
       11. Control means according to claim 9, characterized in that the m read-write circuits are combined into k packages, each package having at the most l read-write circuits with m, l and k integers such that 1≦l≦m and 1≦k≦m, the data bus (21) having l rows, the pth read-write circuit of a package being connected to the pth row of said bus with p being an integer such that 1≦p≦l. 
     
     
       12. Control means according to claim 11, characterized in that it comprises processing means having k processing circuits (17), each connected to a package of read-write circuits (15), the reading, writing and refreshing operations performed by the read-write circuits being selected by means of processing circuits receiving the control signals (20) and supplying the selection signals (35, E, R, L, 37) to the read-write circuits. 
     
     
       13. Control means according to claim 9, characterized in that it comprises a first selection circuit (13) connected at the input to n' address rows (14) and at the output to n row conductors (L i ), with n≦2 n' , for selecting a single row conductor at once. 
     
     
       14. Control means according to any one of the claims 10 and 12, characterized in that it comprises a second selection circuit (19) connected at the input to address rows (18) and at the output to processing means (17) for selecting at least one column conductor (C j ) at once. 
     
     
       15. Control means according to claim 9, characterized in that the first processing circuit (25) comprises a first transistor (24) connected to the first amplifier (27) and use for transferring an information to be written to said first amplifier, as well as a second transistor (26) connected on the one hand to the first transistor (24) and to the first amplifier (27) and on the other handn to the storage means (31), said second transistor (26) being used for transferring a read information to be refresehd to said first amplifier. 
     
     
       16. Control means according to claim 9, characterized in that the storage means (31) comprises a transistor (30) and a capacitor (32) which are interconnected, the transistor also being connected to the second processing circuit (33) and to the second amplifier (29), whilst capacitor (32) is also connected to the first processing circuit (25). 
     
     
       17. Control means according to claim 9, characterized in that one of the first and second amplifiers (27, 29) is an inverting amplifier for applying an alternative signal to the image points. 
     
     
       18. Control process for the control means according to any one of the claims 1 and 9, characterized in that for reading an information at an image point (I ij ) of the display by transmitting it from the image point to the data bus (21) via the read-write circuit (15) corresponding to said image point or for writing an information at said image point by transmitting it in the reverse direction, selection takes place both of the row conductor (L i ) and the column conductor (C j ) corresponding to said image point and for reading an information at an image point of the display by transmitting it from the image point to the corresponding read-write circuit or for refreshing an information at said image point by transmitting it in the reverse direction, selection takes place of at least one row conductor corresponding to said image point, said reading, writing and refresing operations being selected on the basis of control signals. 
     
     
       19. A control means for a matrix display having nxm image points arranged in matrix manner, a first group of n row conductors and a second group of m column conductors carrying appropriate signals for exciting an electro-optical display material, each image point of the display, forming from a capacitor whose dielectric is constituted by the display material, being associated with a row conductor, a column conductor and a switch, each point forming a memory point of the display in which it is possible to write, read and refresh an information, wherein said control means comprises m read-write circuits each connected to a column conductor for reading, writing and refreshing an information at the image points associated with said column conductor, said read-write circuits being combined into k packages, each of which has at the most l read-write circuits, with m, l and k integers such that 1<l<m and 1<k <m, the packages of read-write circuits being connected to a bidirectional data bus of l rows, the pth read-write circuits of each package being connected to the pth row of said bus, with p being an integer such that 1≦p≦l, the reading, writing and refreshing operations performed by the read-write circuits being selected on the basis of control signals, said control means further comprising processing means having k processing circuits, each connected to a package of read-write circuits, the reading, writing and refreshing operations formed by the read-write circuits being selected by means of said processing circuits receiving said control signals and supplying selection signals to the read-write circuits, a first selection circuit connected at the input to n' address rows and at the output to n row conductors with n23 2 n'  for selecting a single row conductor at one time,   a second selection circuit connected at the input to k' address rows and the output to k processing circuits, with k≦2 k'  for selecting a single package of column conductors by choosing a single processing circuit at one time.   
     
     
       20. A control means of a matrix display having nxm image points arranged in matrix manner, a first group of n row conductors and a second group of m column conductors carrying appropriate signals for exciting an electro-optical display material, each image point of the display formed by a capacitor, whose dielectric is constituted by the display material being associated with a row conductor, a column conductor and a switch and each image point constituting a memory point of the display in which it is possible to write, read and refresh an information wherein said control means comprises m read-write circuits, each connected to a column conductor for writing, reading and refreshing an information at the image points associated with said column conductor, the read-write circuits being connected to a bidirectional data bus, the reading, writing and refreshing operations performed by said read-write circuits being selected on the basis of control signals, each read-write circuit comprising writing means which, in the information transfer direction, have a first processing circuit and a first amplifier which are connected together, as well as reading means connected in parallel to the writing means, said reading means having in the information transfer direction, a second amplifier connected both to the storage means and to a second processing circuit, the storage means being also connected to the first processing circuit to enable the read and store information to be refreshed, the first processing circuit transmitting an information from the data bus or storage means to the first amplifier and the second processing circuit transmitting an information from the second amplifier to the data bus, said control means further comprising processing means connected to read-write circuits, the reading, writing and refreshing operations performed by the read-write circuits being selected by said processing means receiving control signals and supplying selection signals to the read-write circuits, said control means further comprising a first selection circuit connected at the input to n' address rows and at the output to n row conductors, with n≦2 n' , for selecting a single row conductor at one time, and a second selection circuit connected at the input to address rows and at the output to said processing means for selecting at least one column conductor at one time.