Digital-to-analog converting apparatus equipped with calibrating function

Abstract

In a D/A converting apparatus which provides a converted analog signal at its output terminal by selectively yielding one or more currents from one or more current sources in accordance with an input digital signal, the current sources are selectively actuated to output the currents and an error in the current of each selected current source is obtained from the output derived at the output terminal in response to the outputting of the current. From the current error of each current source is computed a final error corresponding to each input digital signal and corrected data corresponding to the final error is stored in a corrected data memory, which is read out by the input digital signal. The output thus read out is converted into an analog signal, whereby a correct converted output is obtained.

What is claimed is: 
     
       1. A D/A converting apparatus, for operating in a conversion mode to convert from an input digital signal of a plurality of bits to a respective analog output signal and in a calibration mode for calibrating a group of current sources among a plurality of current sources for providing said analog output signal, said apparatus comprising: a code converting section for receiving a high-order bit signal of a plurality of bits and for outputting a respective equal-weighted bit signal of a larger plurality of bits;   a high-order bit converting section connected to the output of said code converting section for outputting respective equally weighted currents in accordance with respective bits of the equal-weighted bit signal, said high-order bit converting section including a respective plurality of equal-weighted ones of said plurality of current sources for respectively outputting said equally-weighted currents;   a binary bit converting section for receiving a lower-order bit signal of a respective number of bits and, in accordance with each respective bit thereof, for outputting respective binary-weighed currents, said binary bit converting section including a respective number of binary-weighted ones of said plurality of current sources for respectively providing said binary-weighted currents;   a summing amplifier connected to the outputs of said high-order bit and binary bit converting sections for summing the output currents therefrom to produce at an output terminal of said summing amplifier each respective analog output signal;   correcting means for receiving, during said conversion mode, each said input digital signal to be converted into a respective analog output signal, and for outputting respective ones of said high-order and lower-order bit signals, based on a respective set of corrected high-order bit data and corrected lower-order bit data, said correcting means including:   a corrected data memory for receiving as an address a predetermined number of higher-order bits of said input digital signal and reading out therefrom corrected data composed of a set of corrected higher-order and low-order bit data stored therein; and   a digital adder for adding said corrected low-order data read out from said corrected data memory to corresponding low-order bits in said input digital signal to produce summed low-order bit data;   a predetermined number of high-order bits in said corrected higher-order bit data delivered from said corrected data memory being used as said high-order bit signal supplied to said code converting section and a combination of the remaining bits in said corrected higher-order bit data and said summed low-order bit data delivered from said digital adder being used as said lower-order bit signal supplied to said binary bit converting section, respectively;   a microcomputer for generating, during said calibration mode, selection signals to produce, for each said current source to be calibrated, at least one sequence of respective selective states, wherein each said selecting state designates a respective ON or OFF state for at least one respective one of said group of current sources to be calibrated for producing the respective currents to said summing amplifier; and   difference detecting means, connected during said calibration mode, to the output of said summing amplifier, for detecting a difference between the respective analog output signals of each said pair of selecting states;   wherein said microcomputer computes from the respective detected differences current errors for said current sources to be calibrated, computes therefrom each said respective set of said corrected high-order bit data and corrected lower-order bit data for each possible value of the input digital signal, and stores same in said corrected data memory.   
     
     
       2. The apparatus of claim 1, comprising: an offset D/A converter for producing, in response to a set value supplied thereto from said microcomputer, an offset control analog signal; and   an offset current source connected to the output of said offset D/A converter, for producing an offset current in accordance with the offset control analog signal, and for supplying the offset current to said summing amplifier.   
     
     
       3. The apparatus of claim 1, wherein: said input digital signal is composed of the higher-order bits, which are to be supplied as the address for said corrected data memory and which corresponds to those of the current sources to be calibrated, and the low-order bits which are supplied to said adder and which correspond to those of the current sources not to be calibrated; and   said corrected lower-order bit data in said corrected data from said corrected data memory is composed of a corrected intermediate-order bit data having a number of bits corresponding to the number of the binary-weighted current sources to be calibrated and said corrected low-order bit data to be supplied to said adder.   
     
     
       4. The apparatus of claim 1 wherein all of said current sources to be calibrated have output currents of the same polarity, and said correcting means comprises a correction current source of the same polarity as that of the current sources to be calibrated, for supplying a respective correction current to said summing amplifier. 
     
     
       5. The apparatus of claim 1, wherein said microcomputer determines an input-output relationship between the high-order bit signals and the equally-weighted bit signals, so that respective ones of said equal-weighted current sources are selected to optimize the total error of each selected set of at least one equal-weighted current sources according to the respective high-order bit signals, and changes the input-output relationship, between said high-order bit signal and said equal-weighted bit signals of said code converting section, for agreement with the results of the optimization. 
     
     
       6. The apparatus of claim 1, wherein said group of current sources to be calibrated includes at least all but one of said equal-weighted current sources, wherein any of said binary-weighted current sources to be calibrated are those having the largest of said binary-weighted currents, and wherein the largest of said binary-weighted currents is binary-weighted with respect to each said equally-weighted current. 
     
     
       7. The apparatus of claim 1, or wherein said difference detecting means comprises a DC cutting off means connected to said output terminal for substantially cutting off a DC component of said analog output signal, and an A/D converter connected to said DC cutting off means for converting the output from said DC cutting off means during each said sequence of said pairs of selecting states. 
     
     
       8. The apparatus of claim 1, wherein said difference detecting means comprises DC cutting off means, an inverting amplifier, switching means for selectively connecting the input and the output of said inventing amplifier to the input and the output of said DC cutting off means, and an A/D converter for converting the output of said DC cutting off means into digital signals during the setting of each respective pair of said selecting states. 
     
     
       9. The apparatus of claim 1, comprising: analog signal generating means for generating a cancelling analog signal in accordance with a set value supplied from said microcomputer during the setting of at least one selecting state of each of the respective pairs thereof; and   a subtractor for providing each respective difference between the respective analog output signals from said output terminal and the cancelling analog signal to said difference detecting means;   wherein said microcomputer computes the sum of the set value and the output of said difference detecting means obtained during said at least one selecting state to compensate for the cancellation by said cancelling analog signal.   
     
     
       10. A D/A converting apparatus, for operating in a conversion mode to convert from an input digital signal of a plurality of bits to a respective analog output signal and in a calibration mode for calibrating a group of current sources among a plurality of current sources for providing said analog output signal, said apparatus comprising: a code converting section for receiving a high-order bit signal of a plurality of bits and for outputting a respective equal-weighted bit signal of a larger plurality of bits;   a high-order bit converting section connected to the output of said code converting section for outputting respective equally-weighted currents in accordance with respective bits of the equal-weighted bit signal, said high-order bit converting section including a respective plurality of equal-weighted ones of said plurality of current sources for respectively outputting said equally-weighted currents;   a binary bit converting section for receiving a lower-order bit signal of a respective number of bits and, in accordance with each respective bit thereof, for outputting respective binary-weighted currents, said binary bit converting section including a respective number of binary-weighted ones of said plurality of current sources for respectively providing said binary-weighted currents;   a summing amplifier connected to the outputs of said high-order bit and binary bit converting sections for summing the output currents therefrom to produce at an output terminal of the summing amplifier each respective analog output signal;   correcting means for receiving, during said conversion mode, each said input digital signal to be converted into a respective analog output signal, and for outputting respective ones of said high-order and lower-order bit signals, based on a respective set of corrected high-order bit data and corrected lower-order bit data;   a microcomputer for generating, during said calibration mode, selection signals to produce, for each said current source to be calibrated, at least one sequence of respective selecting states, wherein each said selecting state designates a respective ON or OFF state for at least one respective one of said group of current sources to be calibrated for providing the respective currents to said summing amplifier;   difference detecting means, connected, during said calibration mode, to the output of said summing amplifier, for detecting a difference between the respective analog output signals of each said pair of selecting states;   said microcomputer computing from the respective detected differences current errors for said current sources to be calibrated, computing therefrom each said respective set of said corrected high-order bit data and corrected lower-order bit data for each possible value of the input digital signal, and suppling same to said correcting means;   said current sources being calibrated to include all of said equal-weighted current sources;   a predetermined number of higher order bits of each said input digital signal provide a respective higher-order bit signal in correspondence to said current sources to be calibrated, and the remaining lower order bits of each said input digital signal provide a respective input low-order bit signal the bits of which corresponding to those of said binary-weighted current sources which are not to be calibrated;   said correcting means comprising a corrected data memory for respectively storing each said set of corrected high-order and lower-order bit data, said corrected lower-order bit data being composed of a corrected intermediate-order bit data having a number of bits corresponding to the number of the binary-weighted current sources to be calibrated and a corrected lower-order bit data corresponding to those of the binary-weighted current sources not to be calibrated, and an adder for adding said corrected low order bit data from said corrected data memory and said input lower-order bit signal;   said input higher-order bit signal is used as an address for accessing said corrected data memory to read out the corresponding set of said corrected high-order and corrected lower-order bit data, and said correcting means outputs said corrected high-order bit data as said high-order bit signal and the output of the said adder as said lower-order bit signal;   said adder having an overflow output; and   said correcting means including an overflow correction current source connected to receive said overflow output and to provide as an output to said summing amplifier a current having the same weight and the same polarity as the one of any of said binary-weighted current sources to be calibrated which is smallest of said binary-weighted currents.   
     
     
       11. A converter for converting an input digital signal to an output analog signal, comprising: a plurality of current sources for selectively providing respective output currents, including a respective plurality of equal-weighted current sources having equal nominal values for their output currents and a respective plurality of binary-weighted current sources the output currents of which are nominally binary-weighted;   a summer for summing the output currents at least of selected ones of said current sources and to output said output analog signal in correspondence to the summing;   error detecting means for determining error data corresponding to at least relative errors of the nominal values of said output currents of a group of said current sources, based on differences in the output of the summer corresponding to respective predetermined combinations of currents including the respective output currents of said current sources; and   control means for controlling selection of said current sources and for determining from said error data, respective correction data for each value of said input digital signal, said control means comprising:   a corrected data memory for storing the respective correction data and receiving as an address a predetermined number of higher-order bits of said input digital signal and reading out therefrom the respective correction data composed of a set of corrected higher-order and low-order bit data stored therein; and   a digital adder for adding said corrected low-order bit data read out from said corrected data memory to corresponding low-order bits in said input digital signal to produce summed low-order bit data;   a predetermined number of high-order bits in said corrected higher-order bit data delivered from said corrected data memory being used as a high-order bit signal and a combination of the remaining bits in said corrected higher-order bit data and said summed low-order bit data delivered from said digital adder being used as a lower-order bit signal, the high-and lower-order bit signals being used to control the selection of said current sources, output currents from respective ones of said current sources being selected to be supplied to said summer, according to both the respective input digital signal and the respective correction data, for providing said analog output signal.   
     
     
       12. The convertor of claim 11, wherein the output current of each said equally-weighted current source is nominally twice the output current of the one of said binary-weighted current sources having the largest output current, and said group of current sources for which said error data is determined includes at least all but one of said equal-weighted current sources. 
     
     
       13. The converter of claim 12, wherein: said input digital signal is a binary signal, a plurality of the lowest order bits of which have a one-to-one correspondence with a group of any of said binary-weighted current sources having the lowest output currents and for which said correction data is not to be determined, and a plurality of the highest order bits of which correspond to said equal-weighted current sources; and   said group of current sources for which said correction data is determined are associated with a respective plurality of the higher order bits of said input digital signal.   
     
     
       14. The converter of claim 13, said control means comprising: a control section for controlling when said error data and correction data are to be determined and for generating selection commands for selecting the output currents to be provided to said summer for generating the error data;   a code converter for converting from a signal corresponding to said higher order bits of said input digital signal corresponding to said equal-weighted current sources to a respective plurality of individual output signals for selecting the output currents of said equally weighted current sources to be supplied to said summer; and   a multiplexer receiving said individual output signals and said selection commands for providing same to select said equal-weighted current sources according to said microcomputer.   
     
     
       15. The converter of claim 12, 13, comprising a further current source providing a respective output current to said summer, and said control means including means for adjustably setting the output current of said further current source. 
     
     
       16. The converter of claim 12, 13, said control means comprising means for selecting from said equal-weighted current sources on the basis of the respective differences between the actual and nominal values, so as to minimize the errors associated with the respective outputs of said summer corresponding to predetermined values of the said higher order bits of said input digital signal corresponding to said equal-weighted current sources. 
     
     
       17. A converter for converting an input digital signal to an output analog signal, comprising: a plurality of current sources for selectively providing respective output currents, including a respective plurality of equal-weighted current sources having equal nominal values for their output currents and a respective plurality of binary-weighted current sources the output currents of which are nominally binary-weighted, the output current of each said equally-weighted current source is nominally twice the output current of the one of said binary-weighted current sources having the largest output current;   a summer for summing the output currents at least of selected ones of said current sources and to output said output analog signal in correspondence to the sum;   error detecting means for determining error data corresponding to at least relative errors of the nominal values of said output currents of a group of said current sources, based on differences in the output of the summer corresponding to respective predetermined combinations of currents including respective output currents of said current sources, said group of current sources for which said error data is determined includes at least all but one of said equal-weighted current sources, said input digital signal is a binary signal, a plurality of the lowest order bits of which have a one-to-one correspondence with a group of any of said binary-weighted current sources having the lowest output currents and for which said correction data is not to be determined, and a plurality of the highest order bits of which correspond to said equal-weighted current sources, said group of current sources for which said correction data is determined are associated with a respective plurality of the higher order bits of said input digital signal, said error detecting means comprising:   a switch for selectively outputting a first signal corresponding to said output of the summer, a second signal, and ground potential; and   an analog-to-digital converter for converting a signal corresponding to the output of said switch to a digital value;   control means for determining from said error data a respective correction data for each value of said input digital signal;   the output currents from respective ones of said current sources being selected to be supplied to said summing amplifier according to both the respective input digital signal and the respective correction data, and for providing an analog output signal;   a selected one of a subtractor and a high-pass filter connected between the output of said switch and said analog-to-digital converter;   and inverter for inverting said signal corresponding to said output of the summer for supplying said second signal to said switch; and   said subtractor subtracting a selected value from the input to said analog-to-digital converter to allow said converter to have a narrow dynamic range.   
     
     
       18. The converter of claim 17, comprising a subtractor connected to receive said output of the summer and for outputting said signal corresponding to said output of the summer. 
     
     
       19. The converter of claim 17, comprising a flying capacitor circuit connected to receive said output of the summer and to output said second signal to said switch. 
     
     
       20. The converter of claim 17, comprising means for adjusting the gain of said inverter. 
     
     
       21. A converter for converting an input digital signal to an output analog signal, comprising: a plurality of current sources for selectively providing respective output currents, including a respective plurality of equal-weighted current sources having equal nominal values for their output currents and a respective plurality of binary-weighted, current sources the output currents of which are nominally binary-weighted the output current of each said equally-weighted current source is nominally twice the output current of the one of said binary-weighted current sources having the largest output current;   a summer for summing the output currents at least of selected ones of said current sources and to output said output analog signal in correspondence to the sum;   error detecting means for determining error data corresponding to at least relative errors of the nominal values of said output currents of a groups of said current sources, based on differences in the output of the summer corresponding to respective predetermined combinations of currents including respective output currents of said current sources and said group of current sources for which said error data is determined includes at least al but one of said equal-weighted current sources;   control means for determined for said error data respective correction data for each value of said input digital signal;   the output currents from respective ones of said current sources are being selected to be supplied to said summing amplifier according to both the respective input digital signal and the respective correction data for providing an analog output signal;   a further current source having an output current equal to that of the current source having the smallest output current for which said error data is to be determined; and   means for controlling the supply of the output current of said further current source to said summer according to an overflow of said adder.   
     
     
       22. A D/A converting apparatus, for operating in a conversion mode to convert from an input digital signal of a plurality of bits to a respective analog output signal and in a calibration mode for calibrating a group of current sources among a plurality of current sources for providing said analog output signal, said apparatus comprising: a code converting section for receiving a high-order bit signal of a plurality of bits and for outputting a respective equal-weighted bit signal of a larger plurality of bits;   a high-order bit converting section connected to the output of said code converting section for outputting respective equally weighted currents in accordance with respective bits of the equal-weighted bit signal, said high-order bit converting section including a respective plurality of equal-weighted ones of said plurality of current sources for respectively outputting said equally-weighted currents;   a binary bit converting section for receiving a lower-order bit signal of a respective number of bits and, in accordance with each respective bit thereof, for outputting respective binary-weighted currents, said binary bit converting section including a respective number of binary-weighted ones of said plurality of current sources for respectively providing said binary-weighted currents, at least one of said binary-weighted current sources is to b e calibrated and the output currents of each said binary-weighted current source to be calibrated and of a first one of said equally-weighted current sources have the same polarity;   current subtracting means for supplying a current of the same value but of opposite polarity as the output current of said first equally-weighted current source to said summing amplifier during the occurrence of each respective pair of said selecting states corresponding to each said binary-weighted current source to be calibrated;   a summing amplifier connected to the outputs of said high-order bit and binary bit converting sections for summing the output currents therefrom to produce at an output terminal of the summing amplifier each respective analog output signal;   correcting means for receiving, during said conversion mode, each said input digital signal to be converted into a respective analog output signal, and for outputting respective ones of said high-order and lower-order bit signals, based on a respective set of corrected high-order bit data and corrected lower-order bit data;   a microcomputer for generating, during said calibration mode, selection signals to produce, for each said current source to be calibrated, at least one sequence of respective selecting states, wherein each said selecting state designates a respective ON or OFF state for at least one respective one of said group of current sources to be calibrated for providing the respective currents to said summing amplifier;   difference detecting means connected, during said calibration mode, to the output of said summing amplifier for detecting a difference between the respective analog output signals of each said pair of selecting states; and   said microcomputer computing from the respective detected differences current errors for said current sources to be calibrated, computing therefrom each said respective set of said corrected high-order bit data and corrected lower-order bit data for each possible value of the input digital signal, and suppling same to said correcting means;   said first one of said equal-weighted current sources is used as a reference current source; and   said microcomputer producing said pairs of selection signals such that, in a first selecting state of the respective pair of said selecting states corresponding to each said binary-weighted current source to be calibrated, said reference current source and the respective binary-weighted current source to be calibrated are turned ON, and, in the other selecting state of the respective pair of selecting states, the respective binary-weighted current source to be calibrated and all the binary-weighted current sources with higher output currents are turned ON.   
     
     
       23. The apparatus of claim 22, wherein said current subtracting means comprises a plurality of predetermined ones of said equal-weighted current sources excluding said reference current source, and and offset current source for producing a current equal to but opposite in polarity from the sum of said predetermined ones of said equal-weighted current sources and said reference current source. 
     
     
       24. A/D converting apparatus, for operating in a conversion mode to convert from an input digital signal of a plurality of bits to a respective analog output signal and in a calibration mode for calibrating a group of current sources among a plurality of current sources for providing said analog output signal, said apparatus comprising: a code converting section for receiving a high-order bit signal of a plurality of bits and for outputting a respective equal-weighted bit signal of a larger plurality of bits;   a high-order bit converting section connected to the output of said code converting section for outputting respective equally-weighted currents in accordance with respective bits of the equal-weighted bit signal, said high-order bit converting section including a respective plurality of equal-weighted ones of said plurality of current sources for respectively outputting said equally-weighted currents;   a binary bit converting section for receiving a lower-order bit signal of a respective number of bits and, in accordance with each respective bit thereof, for outputting respective binary-weighted currents, said binary bit converting section including a respective number of binary-weighted ones of said plurality of current sources for respective providing said binary-weighted currents;   a summing amplifier connected to the outputs of said high-order bit and binary bit converting sections for summing the output currents therefrom to produce at an output terminal of the summing amplifier each respective analog output signal;   correcting means for receiving, during said conversion mode, each said input digital signal to be converted into a respective analog output signal, and for outputting respective ones of said high-order and lower-order bit signals, based on a respective set of corrected high-order bit data and corrected lower-order bit data;   a microcomputer for generating, during said calibration mode, selection signals to produce, for each said current source to be calibrated, at least one sequence of respective selecting states, wherein each said selecting state designates a respective ON or OFF state for at least one respective one of said group of current sources to be calibrated for providing the respective currents to said summing amplifier;   difference detecting means connected, during said calibration mode, to the output of said summing amplifier for detecting a difference between the respective analog output signals of each said pair of selecting states;   said microcomputer computing from the respective detected differences current errors for said current sources to be calibrated, computing therefrom each said respective set of said corrected high-order bit data and corrected lower-order bit data for each possible value of the input digital signal, and suppling same to said correcting means;   a reference current source for producing a reference current equal to but opposite in polarity to the current of a first one of said equal-weighted current sources; and   the current sources to be calibrated including at least one of said binary-weighted current sources with the largest of said binary-weighted currents, and said microcomputer producing said selection signals such that in a first one of the respective pair of selecting states for each respective binary-weighted current source to be calibrated, the reference current source and any of the binary-weighted current sources with a larger binary-weighted current are turned ON and in the other selecting state of the respective pair only the respective binary-weighted current source to be calibrated is turned ON.