Active matrix display screen permitting the display of gray levels

Abstract

A single signal is produced, which includes a pedestal and a ramp. This signal is supplied to a column control circuit which transmits the voltage to each column for a time which can assume a number of discrete values between t 1 , the pedestal duration, and T L , the addressing time of one row. For t 1 , the black level is obtained, for T L the white level and between them, various gray levels.

What is claimed is: 
     
       1. An active matrix display screen comprising a first wall on which are deposited a matrix of N by P electrodes forming the first plates of capacitors, N addressing columns and P addressing rows, NP control transistors each having a drain (D), a gate (G) and a source (S), the drain (D) of each transistor being connected to the plate of one of the capacitors, the source to one of the columns and the gate to one of the rows; a second wall on which is deposited a counterelectrode forming the second plate of the capacitors; a first control circuit able to successively apply to the N rows a voltage Ve able to make the transistors of each row on for a time T L , the control of the N rows constituting a frame of duration Tr=NT L  ; a second control circuit able to apply to the counterelectrode a voltage Vce successively assuming two values, namely a value 0 and and a value Vc, the voltage Vce passing from one to the other of these values either following each frame, or following each row; and a third control circuit able to apply to the P columns for the entire control time of a row, a set of P voltages, said screen being characterized in that the third control circuit comprises a circuit supplying a voltage Vcb having a pedestal of duration t 1  of value equal to the voltage Vce applied to the counterelectrode and for a duration t 2  a ramp-like voltage passing linearly from said voltage Vce to a voltage differing from Vce by a quantity Vc, the total duration t 1  +t 2  of the voltage Vcb being equal to the control time T L  of a row; and secondary column control circuits connected between said third control circuit and each column and which transmit to each column said voltage Vcb for a time which can assume a series of discrete values between t 1 , in which case a black display is obtained, and T L  in which case a white display is obtained, each intermediate discrete value between t 1  and T L   corresponding to a gray display. 
     
     
       2. A display screen according to claim 1, wherein the third control circuit is constituted by P transistors having a source connected to the circuit supplying the voltage Vcb, a drain connected to one of the P columns and an gate connected to a operating circuit able to supply a voltage for controlling the turning on of the transistor for a time which is a function of the gray level to be displayed. 
     
     
       3. A display screen according to claim 2 wherein said operating circuit is able to supply a voltage for controlling the turning on of P transistors is constituted by P shift registers having n cells each, the first cell of each register being connected to the gate of one of the transistor, each register containing n bits, whereof the first is always equal to 1 and the following bits to 0 or 1, all these n bits characterizing a gray level, said registers being controlled by a common clock of period t 1 , which is equal to said pedestal duration and which control the shift of the bits into each register, the duration t 1  being such that nt 1  is equal to the total row control duration T L .