Hot electron collector for a LDD transistor

Abstract

A lightly-doped drain (LDD) structure has conductive shield overlying the lightly-doped drain and source portions to collect and/or remove hot carriers which can otherwise cause instabilities such as gain degradation and threshold voltage shifts in short-channel MOS devices. The hot carriers eventually deteriorate the performance of the transistor to the point where the transistor provides insufficient performance. Thus, the lifetime of a transistor is affected by the degradation caused by the formation of hot carriers. The lifetime is increased by collecting the hot carriers in the conductive material over the lightly-doped source and drain.

I claim: 
     
       1. A transistor formed in an active region of a substrate, comprising: a first insulator layer on the active region;   a gate overlying the first insulator layer at an intermediate portion of the active region leaving a first portion and a second portion of the active region uncovered by the gate, said gate having a first side and a second side, said first and second sides aligned with said first and second portions, respectively, of the active region;   a second insulator layer coating the first and second sides of the gate;   a lightly-doped source region in the first portion of the active region and aligned substantially with the first side of the polysilicon gate;   a lightly-doped drain region in the second portion of the active region aligned substantially with the second side of the polysilicon gate;   a channel region in the active region, under the gate, and between the lightly-doped source region and the lightly-doped drain region;   a first heavily-doped region in the first portion of the active region, offset from the first side of the polysilicon gate, and adjoining the lightly-doped source region;   a second heavily-doped region in the second portion of the active region, offset from the second side of the polysilicon gate, and adjoining the lightly-doped drain region;   a first conductive strip adjoining the second insulator layer on the first side of the gate, over at least a portion of the lightly-doped source region, and separated from the lightly-doped source region by the first insulator layer; and   a second conductive strip adjoining the second insulator layer on the second side of the gate, over at least a portion of the lightly-doped drain region, and separated from the lightly-doped drain region;   a first conductive layer over the source region and in contact with the first conductive strip and the source region; and   a second conductive layer over the drain region and in contact with the first conductive strip and the drain region.   
     
     
       2. The transistor of claim 1 wherein the first insulator layer is further characterized as being oxide with silicon impregnated portions on the surface thereof and in contact with the first conductive layer and the second conductive layer. 
     
     
       3. The transistor of claim 1 wherein the first and second conductive strips are polysilicon. 
     
     
       4. The transistor of claim 1 wherein the first conductive strip is characterized has having a vertical portion adjoining the second insulator layer and a horizontal portion adjoining the first insulator layer. 
     
     
       5. The transistor of claim 1 wherein the gate has a thickness measured along the first side thereof and the first conductive strip has a horizontal dimension along the first insulator layer and a vertical dimension along the first side of the gate, said vertical dimension being substantially less than the thickness of the gate and substantially less than the horizontal dimension. 
     
     
       6. The transistor of claim 1 wherein the first conductive strip is characterized as being a layer parallel with the surface of the substrate and of uniform thickness. 
     
     
       7. A transistor formed in an active region of a substrate, comprising: a first insulator layer on a portion of the active region;   a gate overlying the first insulator layer at an intermediate portion of the active region leaving a first portion and a second portion of the active region uncovered by the gate, said gate having a first side and a second side, said first and second sides aligned with said first and second portions, respectively, of the active region;   a second insulator layer coating the first and second sides of the gate;   a lightly-doped source region in the first portion of the active region and aligned substantially with the first side of the polysilicon gate;   a lightly-doped drain region in the second portion of the active region aligned substantially with the second side of the polysilicon gate;   a channel region in the active region, under the gate, and between the lightly-doped source region and the lightly-doped drain region;   a first heavily-doped region in the first portion of the active region, offset from the first side of the polysilicon gate, and adjoining the lightly-doped source region;   a second heavily-doped region in the second portion of the active region, offset from the second side of the polysilicon gate, and adjoining the lightly-doped drain region;   a first conductive strip adjoining the insulator coating on the first side of the gate and over at least a portion of the lightly-doped source;   a first insulating portion under the first conductive strip;   a second conductive strip adjoining the insulator coating on the second side of the gate and over at least a portion of the lightly-doped source;   a second insulating portion under the second conductive strip;   an electrical contact between the first conductive strip and the first heavily-doped region; and   an electrical contact between the second conductive strip and the second heavily-doped region.   
     
     
       8. The transistor of claim 7 wherein the first conductive strip is formed by the steps of: implanting silicon onto the first insulating portion; and   performing selective deposition of polysilicon to form the first conductive strip.   
     
     
       9. The transistor of claim 7 wherein the first and second conductive strips are formed by the steps of: depositing polysilicon over at least the first and second lightly-doped regions, the first and second heavily-doped regions, and the gate;   forming a first sidewall spacer on a first portion of the polysilicon, said first sidewall spacer overlying the first lightly-doped region and leaving the first heavily-doped region uncovered by the first sidewall spacer, and located beside the first side of the gate and separated therefrom by the second insulating layer;   forming a second sidewall spacer on a second portion of the polysilicon, said second sidewall spacer overlying the second lightly-doped region and leaving the second heavily-doped region uncovered by the first sidewall spacer, and located beside the first side of the gate and separated therefrom by the second insulating layer; and   etching the polysilicon over the gate and the first and second heavily-doped regions using the first and second sidewall spacers as masks.   
     
     
       10. The transistor of claim 7 wherein the first insulator layer is further characterized as being oxide with silicon impregnated portions on the surface thereof and in contact with the first conductive layer and the second conductive layer. 
     
     
       11. The transistor of claim 7 wherein the first and second conductive strips are polysilicon. 
     
     
       12. The transistor of claim 7 wherein the first conductive strip is characterized has having a vertical portion adjoining the second insulator layer and a horizontal portion adjoining the first insulator layer. 
     
     
       13. The transistor of claim 7 wherein the gate has a thickness measured along the first side thereof and the first conductive strip has a horizontal dimension along the first insulator layer and a vertical dimension along the first side of the gate, said vertical dimension being substantially less than the thickness of the gate and substantially less than the horizontal dimension. 
     
     
       14. The transistor of claim 7 wherein the first conductive strip is characterized as being a conductive layer parallel with the surface of the substrate and of uniform thickness.