Semiconductor device to prevent out-diffusion of impurities from one conductor layer to another

Abstract

A semiconductor device includes a first conductor layer into which is diffused an impurity for lowering the resistance, and a second conductor layer provided on the upper side of the first conductor layer through a stopper layer which suppresses the out-diffusion of the impurity. By virtue of the existence of the stopper layer, it is possible to inhibit the above-described impurity from being diffused into the second conductor layer. In SRAM, resistance variations between high-resistance elements which correspond to the second conductor layer can be suppressed, so that it is possible to prevent the lowering of the yield with respect to the electrical reliability. In SRAM, further, the resistance of the high-resistance elements is not lowered; therefore, it is possible to reduce the power consumption.

What is claimed is: 
     
       1. A semiconductor device comprising: a first conductor layer being comprised of a polycrystalline silicon film into which is diffused an impurity for lowering the resistance thereat;   an insulating film being formed on said first conductor layer and having a contact hole at a predetermined portion of said insulating film above said first conductor layer;   a stopper layer being provided on said first conductor layer at least at said predetermined portion where said contact hole is formed; and   a second conductor layer being comprised of a polycrystalline silicon film provided on an upper side of said insulating film and electrically connected to said first conductor layer through said contact hole and said stopper layer, said second conductor layer having a predetermined portion thereof provided as a resistance element, wherein said stopper layer is such that it inhibits the impurity contained in said first conductor layer from being diffused into said second conductor layer.   
     
     
       2. A semiconductor device according to claim 1, wherein said first conductor layer and said predetermined portion of said second conductor layer comprise a gate electrode of a MISFET and a load resistance element in a memory cell of a SRAM, respectively. 
     
     
       3. A semiconductor device according to claim 2, wherein said second conductor layer is comprised of a first substantially non-doped portion for forming said resistance element and a second portion which has a high concentration of an impurity for forming a wiring. 
     
     
       4. A semiconductor device according to claim 3, wherein said stopper layer is comprised of a conductor layer. 
     
     
       5. A semiconductor device according to claim 4, wherein said stopper layer is formed from one of a polycrystalline silicon film and a single crystal film. 
     
     
       6. A semiconductor device having memory cells each of which including first and second inverters each comprising a series circuit of a driving MISFET and a load element, output terminals of said first and second inverters being respectively connected to input terminals of said second and first inverters, said driving MISFETs of said first and second inverters having gate electrodes comprised of respective portions of a first polycrystalline silicon film into which is diffused an impurity for lowering its resistance, and wherein there is included an insulating film which is formed so as to extend over said first polycrystalline silicon film and which insulating film has contact holes formed at predetermined portions thereof including at portions directly overlying said first polycrystalline silicon film, and a second polycrystalline silicon film which is formed on said insulating film and which is extended so as to be in electrical contact with said first polycrystalline silicon film via a stopper layer through respective ones of said contact holes, said stopper layer being provided on said first polycrystalline silicon film at least at said predetermined portion where said contact hole is formed so as to inhibit the impurity contained in said first polycrystalline silicon film of said driving MISFETs from being diffused into said load elements of said first and second inverters. 
     
     
       7. A semiconductor device according to claim 6, wherein said second polycrystalline silicon film comprises a first substantially non-doped portion for forming said load element and a second portion which has a high concentration of an impurity. 
     
     
       8. A semiconductor device according to claim 7, wherein said stopper layer is comprised of a conductor layer. 
     
     
       9. A semiconductor device according to claim 8, wherein said conductor layer is formed from a polycrystalline silicon film. 
     
     
       10. A semiconductor device according to claim 9, wherein said second polycrystalline silicon film is correspondingly associated with said first and second inverters, and wherein said second polycrystalline silicon film is formed over said first polycrystalline silicon film and is electrically connected to said first polycrystalline silicon film of said second and first inverters, respectively. 
     
     
       11. A semiconductor device according to claim 10, wherein said first polycrystalline silicon film, correspondingly associated with said first and second inverters, is connected to the respective load element and the drain region corresponding to the driving MISFET of said second and first inverters, respectively. 
     
     
       12. A semiconductor device according to claim 11, wherein said memory cell constitutes a memory cell of a static random access memory. 
     
     
       13. A semiconductor device according to claim 12, wherein said gate electrodes of said driving MISFETs are comprised of one of a refractory metal film and a refractory metal silicide film provided on said first polycrystalline silicon film. 
     
     
       14. A semiconductor device according to claim 13, wherein said stopper layer has the same pattern shape as the gate electrode of said driving MISFETs of said first and second inverters. 
     
     
       15. A semiconductor device according to claim 6, wherein said memory cell constitutes a memory cell of a static random access memory, and wherein said gate electrodes of said driving MISFETs are comprised of one of a refractory metal film and a refractory metal silicide film provided on said first polycrystalline silicon film. 
     
     
       16. A semiconductor device according to claim 4, wherein said stopper layer is formed from one of a polycrystalline silicon film and a single crystal silicon film. 
     
     
       17. A semiconductor device according to claim 4, wherein said stopper layer has an out-diffusion of impurities coefficient which is substantially lower than that of said first conductor layer. 
     
     
       18. A semiconductor device having memory cells each of which including first and second inverters each comprising a series circuit of a driving MISFET and a load element, output terminals of said first and second inverters being respectively connected to input terminals of said second and first inverters, said driving MISFETs of said first and second inverters having gate electrodes comprised of one of a refractory metal film and a refractory metal silicide film provided on a first polycrystalline silicon film into which is diffused an impurity for lowering its resistance, and wherein there is included an insulating film which is formed so as to extend over said first polycrystalline silicon film and which insulating film has contact holes formed at predetermined portions thereof including at portions directly overlying said first polycrystalline silicon film, and a second polycrystalline silicon film which is formed on said insulating film and which is electrically connected to the respective load element is extended so as to be in electrical contact with said first polycrystalline silicon film via a stopper layer through respective ones of said contact holes, said stopper layer being provided on said one of a refractory metal film and a refractory metal silicide film at least at a predetermined portion where a contact hole is formed so as to inhibit the impurity contained in said first polycrystalline silicon film of said driving MISFETs from being diffused into said load elements of said first and second inverters. 
     
     
       19. A semiconductor device according to claim 18, wherein said second polycrystalline silicon film comprises a first substantially non-doped portion from forming said load element and a second portion which has a high concentration of an impurity. 
     
     
       20. A semiconductor device according to claim 19 wherein said stopper layer is comprised of a conductor layer. 
     
     
       21. A semiconductor device according to claim 20, wherein said conductor layer is formed from a polycrystalline silicon film. 
     
     
       22. A semiconductor device according to claim 21, wherein said second polycrystalline silicon film is correspondingly associated with said first and second inverters, and wherein said second polycrystalline silicon film is formed over said first polycrystalline silicon film and is electrically connected to said first polycrystalline silicon film of said second and first inverters, respectively. 
     
     
       23. A semiconductor device according to claim 22, wherein said first polycrystalline silicon film, correspondingly associated with said first and second inverters, is connected to the respective load element and the drain region corresponding to the driving MISFET of said second and first inverters, respectively. 
     
     
       24. A semiconductor device according to claim 23, wherein said memory cell constitutes a memory cell of a static random access memory.