Photovoltaic isolator and process of manufacture thereof

Abstract

A photovoltaic isolator consists of a stack of semiconductor wafers which are alloyed together by an aluminum silicon alloy foil. Each of the wafers consists of a very high resistivity P-type body having P+ and N+ diffusions on its opposite surfaces. The wafers are stacked with the same forward conduction polarity. Individual photoisolator stacks are sliced from the completed stack to any desired dimension. Each individual stack is mounted with a light source, preferably an LED, which is arranged to illuminate the edge of each wafer within the stack. The LED and stack are spaced by about 30 mils so that high dielectric isolation exists between the LED and photovoltaic stack. Energization of the LED will produce a relatively high output short circuit current from the stack and a high output voltage which can turn a power MOSFET on very quickly after the energization of the LED.

What is claimed is: 
     
       1. A photovoltaic isolator comprising, in combination: an LED radiation source; a photovoltaic stack having the form of a rectangular parallelepiped and which has series connected junctions extending to the vertical side of said stack; and a housing for containing said LED and photovoltaic said stack; said LED being spaced from said photovoltaic stack by greater than about 20 mils to obtain a desired dielectric isolation between said LED and said photovoltaic stack; said LED being positioned at the center of one vertical side of said stack and arranged to illuminate at least said one vertical side of said stack; said stack having a relatively short height, less than about 150 mils to improve uniformity in illumination of said at least one vertical side of said stack by said LED. 
     
     
       2. A photovoltaic isolator for providing gate drive to an insulated gate of a FET-type device, comprising, in combination: an input LED radiation source; a photovoltaic stack having the form of a rectangular parallelepiped with first, second, third and fourth vertical sides and first and second electrodes on the remaining two sides of said stack, respectively; and an optically transmissive housing for containing said LED and said photovoltaic stack and providing an optical path through said housing for direct radiation from said LED to said first vertical side and for reflected radiation from said LED to said second vertical side; said LED being orthogonally spaced from said first vertical side by greater than about 20 mils to obtain a desired dielectric isolation between said LED and said photovoltaic stack; said LED being positioned at the center of said first vertical side of said stack; said housing having a sufficient height above said second vertical side to permit said second vertical side to receive reflected radiation from said LED; said stack having a relatively short height, less than about 150 mils to improve uniformity in illumination of said first vertical side of said stack by said LED; said first and second electrodes of said stack being directly connectable to an insulated gate of a FET-type device, whereby said photovoltaic stack can comprise the sole electrical power source for driving said gate. 
     
     
       3. The photovoltaic isolator of claim 2, wherein said stack consists of a vertical stack of a plurality of identical monocrystalline silicon chips; each of said chips comprising a thin body having flat first and second parallel surfaces; each of said chips having a main body portion of very high lifetime P type conductivity material; each of said chips having a shallow N type diffusion extending into its said first surface to a uniform depth across substantially the full surface area of said first surface; each of said chips having a shallow P+ layer of conductivity substantially higher than that of said P type body extending into its said second surface to a uniform depth across substantially the full surface area of said second surface; a plurality of high conductivity layers disposed between adjacent chips of said stack for mechanically and electrically connecting said stack together with the forward conduction directions of each of said chips being in the same direction; the edge of the junctions between said P type body and said N type layer of each of said chips being exposed along at least one portion of one surface of the vertical sides of said stack to enable the edge illumination of said stack; and first and second electrodes on the opposite ends of said stack. 
     
     
       4. The device of claim 3, wherein the thickness of each of said chips is less than the average diffusion length of minority carriers which are produced in said body in response to application of radiation to said vertical sides of said chip; said P+ layer acting as a reflector to reflect minority change carriers toward the collection junction formed by said P type body and said N type layer. 
     
     
       5. The device of claim 3 wherein each of said chips has a shallow P+ diffusion layer of conductivity substantially higher than that of said P type body extending into its second surface to a uniform depth across substantially the full surface area of said second surface. 
     
     
       6. The device of claim 3 or 5, wherein said N+ layer has a conductivity defined by the presence of from about 1×10 20  to 4×10 20  impurity atoms per cubic centimeter at said first surface; whereby said N+ layer will not be converted to the P conductivity type when alloyed to an aluminum foil. 
     
     
       7. The device of claim 3 or 5, wherein said plurality of high conductivity layers consist of a foil having a thickness of about 1 mil and is of a material selected from the group consisting of aluminum, aluminum alloys and an aluminum silicon eutectic. 
     
     
       8. The device of claim 7, wherein said chips have a thickness less than about 9 mils and wherein said stack consists of less than about 15 chips. 
     
     
       9. The device of claim 3 or 5, wherein said chips have a thickness less than about 9 mils wherein said stack consists of less than about 15 chips. 
     
     
       10. The device of claim 3 or 5, wherein said N+ layer is formed from a diffused phosphorus impurity; said phosphorus impurity acting as a getter to metal ions within said P type body, thereby to increase the lifetime of said P type body. 
     
     
       11. The device of claim 3 or 5, wherein said slab has the shape of a rectangular parallelepiped. 
     
     
       12. The photovoltaic isolator of claim 2, wherein said housing has a height above said second surface of about three times the height of said first side so as to increase the amount of radiation reaching said second surface from said LED that is reflected only once. 
     
     
       13. The photovoltaic isolator of claim 2 or 12, further including a support with a major surface which is flat, and wherein said photovoltaic stack and said LED lie atop said major surface, with said fourth vertical side of said stack lying on said major surface in confronting relation thereto. 
     
     
       14. The photovoltaic isolator of claim 13, wherein said optically transmissive housing adjoins said first, second and third vertical sides of said stack and optically couples said first through third vertical sides to said LED. 
     
     
       15. The photovoltaic isolator of claim 2 or 12, further including a reflective coating atop said optically transmissive housing. 
     
     
       16. The process of claim 15, wherein phosphorus is used for the impurity to form said opposite conductivity type layer, wherein said phosphorus acts as a getter to metal ions in said one conductivity type wafers, thereby to increase the lifetime of said one conductivity type body. 
     
     
       17. The process of claim 15 or 5, wherein said thin conductive layers consist of thin foils of a material selected from the group consisting of aluminum and aluminum containing materials. 
     
     
       18. The process of claim 15, wherein said reflective coating comprises titanium dioxide. 
     
     
       19. The process of forming a photovoltaic isolator for providing gate drive to an insulated gate of a FET-type device, the process comprising the steps of: (a) forming a photovoltaic stack by: (i) diffusing a thin high conductivity layer of one conductivity type into the first surface of a plurality of wafers of said one conductivity type material;   (ii) diffusing a thin layer of an opposite conductivity type into the opposite surface of said wafers;   (iii) stacking less than about 20 of said wafers atop one another with the forward conduction direction of their junctions in the same direction, with thin conductive layers of connective material disposed between adjacent wafers;   (iv) treating said stack to secure said adjacent wafers together by adherence of said layers of connective material to adjacent wafers of said stack;   (v) cutting vertically through said stack of wafers to form a plurality of individual slabs having the shape of rectangular parallelepipeds with first, second, third and fourth successive sides and with the edge of the junctions of said wafers exposed at the sides of said slabs; and   (vi) forming first and second electrodes on the remaining two sides of said stack, respectively; said first and second electrodes being directly connectable to an insulated gate of a FET-type device, whereby said photovoltaic stack can comprise the sole electrical power source for driving said gate;     (b) placing an LED in an orthogonally offset position from said first side; and   (c) forming an optically transmissive housing over said first and second sides of said photovoltaic stack and said LED so as to provide an optical path through said housing for direct radiation from said LED to said first side and for reflected radiation from said LED to said second side; said housing being formed with a sufficient height above said second side to permit said second side to receive a substantial amount of reflected radiation from said LED compared to the direct radiation received by said first side.   
     
     
       20. The process of claim 19, wherein said housing is formed to a height above said second side of about three times the height of said first side so as to increase the amount of radiation reaching said second surface form said LED that is reflected only once. 
     
     
       21. The process of claim 19 or 20, further including the step of placing said photovoltaic stack and said LED atop a flat surface of a substrate, with said fourth side of said stack lying atop said flat surface in confronting relation thereto. 
     
     
       22. The process of claim 21, further including the step of forming said optically transmissive housing additionally over said third side of said photovoltaic stack to thereby optically couple said LED to said third side. 
     
     
       23. The process of claim 19 or 20, further including the step of forming a reflective coating over said housing. 
     
     
       24. The process of claim 19 or 20, further comprising the step of forming a reflective coating over said housing which includes titanium dioxide. 
     
     
       25. A photovoltaic stack, comprising: (a) a vertical stack including a plurality of identical monocrystalline silicon chips, each of the chips having: (i) a main body portion of P-type material with a resistivity higher than about 30 ohm-centimeters; and   (ii) a relatively shallow diffusion layer of N+ material extending to a uniform depth in one main surface in each chip;     (b) a respective high conductivity layer disposed between each adjacent pair of chips in the stack;   (c) the edges of each junction between the P type body and the N+ layer of each chip being exposed along at least one portion of one surface of the vertical sides of the stack; and   (d) a respective electrode on each end of the stack.   
     
     
       26. The photovoltaic stack of claim 25, wherein the stack has the form of a rectangular parallelepiped. 
     
     
       27. The photovoltaic stack of claim 25, wherein said vertical stack of chips is less than about 150 mils in height. 
     
     
       28. The photovoltaic stack of claim 25, wherein said plurality of said chips in said vertical stack is less than about 20. 
     
     
       29. The photovoltaic stack of claim 25, wherein said chips have a thickness less than about 9 mils and wherein said stack consist of less than about 15 chips. 
     
     
       30. The photovoltaic stack of claim 25, wherein said N+ layer as a conductivity defined by the presence of from about 1×10 20   to 4×10 20  impurity atoms per cubic centimeter at said one main surface; w hereby said N+ layer will not be converted to the P conductivity type when allowed to an aluminum foil. 
     
     
       31. The photovoltaic stack of claim 25, wherein each of said chips has a shallow P+ diffusion layer of conductivity substantially higher than that of said main body portion of P-type material extending into a second surface in each chip to a uniform depth across substantially the full surface area of said second surface. 
     
     
       32. The photovoltaic stack of claim 25, wherein said respective high conductivity layer consists of a foil having a thickness of about 1 mil and is of a material selected from the group consisting of aluminum, aluminum alloys and an aluminum silicon eutectic. 
     
     
       33. The photovoltaic stack of claim 25, wherein said N+ layer is formed from a diffused phosphorus impurity; said phosphorus impurity acting as a getter to metal ions within said main body portion of P-type material, thereby to increase the lifetime of said main body portion. 
     
     
       34. A photovoltaic isolator for providing gate drive to an insulated gate of a FET-type device, comprising, in combination: an input LED radiation source;   a photovoltaic stack comprising a vertical stack of a plurality of identical monocrystalline silicon chips, each of the chips having a main body portion of P-type material with a resistivity higher than about 30 ohm-centimeters, and a relatively shallow diffusion layer of N+ material extending to a uniform depth in one main surface in each chip; a respective high conductivity layer disposed between each adjacent pair of chips in the stack; the edge of each junction between the P-type body and the N+ layer of each chip being exposed along at least one portion of one surface of the vertical sides of the stack; said photovoltaic stack having the form of a rectangular parallelepiped with first, second, third and fourth vertical sides and first and second electrodes on the remaining two sides of said stack, respectively;   an optically transmissive housing for containing said LED and said photovoltaic stack and providing an optical path through said housing for direct radiation from said LED to said first vertical side and for reflected radiation from said LED to said second vertical side; said LED being orthogonally spaced from said first vertical side by greater than about 20 mils to obtain a desired dielectric isolation between said LED and said photovoltaic stack; said LED being positioned at the center of said first vertical side of said stack; said housing having a sufficient height above said second vertical side to permit said second vertical side to receive reflected radiation from said LED;   said stack having a relatively short height, less than about 150 mils to improve uniformly in illumination of said first vertical side of said stack by said LED; and   said first and second electrodes of said stack being directly connectable to an insulated gate of a FET-type device, whereby said photovoltaic stack can comprise the sole electrical power source for driving said gate.   
     
     
       35. The photovoltaic isolator of claim 34, wherein said housing has a height above said second surface of about three times the height of said first side so as to increase the amount of radiation reaching said second surface from said LED that is reflected only once. 
     
     
       36. The photovoltaic isolator of claim 34, further including a support with a major surface which is flat, and wherein said photovoltaic stack and said LED lie atop said major surface, with said fourth vertical side of said stack lying on said major surface in confronting relation thereto. 
     
     
       37. The photovoltaic isolator of claim 36, wherein said optically transmissive housing adjoins said first, second and third vertical sides of said stack and optically couples said first through third vertical sides to said LED. 
     
     
       38. The photovoltaic isolator of claim 34, further including a reflective coating atop said optically transmissive housing. 
     
     
       39. The photovoltaic isolator of claim 38, wherein said reflective coating comprises titanium dioxide. 
     
     
       40. The photovoltaic isolator of claim 34, wherein said N+ layer has a conductivity defined by the presence of from about 1×10 20  to 4×10 20  impurity atoms per cubic centimeter at said first surface; whereby said N+ layer will not be converted to P conductivity when alloyed to an aluminum foil. 
     
     
       41. The photovoltaic isolator of claim 34, wherein said respective high conductivity layers each consists of a foil having a thickness of about 1 mil and is of a material selected from the group consisting of aluminum, aluminum alloys and an aluminum silicon eutectic. 
     
     
       42. The photovoltaic isolator of claim 34, wherein said chips have a thickness less than about 9 mils and wherein said stack consists of less than about 15 chips. 
     
     
       43. The photovoltaic isolator of claim 34, wherein said N+ layer is formed from a diffused phosphorus impurity; said phosphorus impurity acting as a getter to metal ions within said P type body, thereby to increase the lifetime of said P type body.