Nand cell type programmable read-only memory with common control gate driver circuit

Abstract

A NAND cell type EEPROM has a substrate, parallel bit lines formed above the substrate, and a memory cell section including an array of NAND type cell units associated with the same corresponding bit line. Each of the NAND type cell units has a series-circuit of eight data storage transistors and at least one selection transistor. Each data storage transistor has a floating gate for storing carriers injected thereinto by tunneling and a control gate respectively connected to word lines. A control gate driver circuit is provided in common for all the NAND type cell units that are assisted with the same bit line. Transfer gates are connected between the common driver circuit and the NAND cell units.

What is claimed is: 
     
       1. A non-volatile semiconductor memory device comprising: a substrate;   parallel data transmission lines formed above said substrate;   a memory cell section including an array of NAND type cell units associated with a corresponding one of said data transmission lines;   each of said NAND type cell units having a series-circuit of a preselected number of data storage transistors with control gates and a switching transistor; and   a control gate driver circuit formed on said substrate and provided in common for a plurality of certain NAND type cell units specified from among said NAND type cell units associated with the corresponding data transmission line.   
     
     
       2. The device according to claim 1, wherein each of said data storage transistors has a carrier storage layer insulatively provided above said substrate, and wherein said switching transistor has a selection gate and is provided between said series-circuit of data storage transistors and a corresponding data transmission line. 
     
     
       3. The device according to claim 2, wherein said control gate driver circuit is connected in common with said NAND type cell units associated with the same data transmission line. 
     
     
       4. The device according to claim 3, further comprising: transfer gate means provided between said NAND type cell units and said control gate driver circuit, for selectively connecting corresponding ones of the control gates of said NAND type cell units with said control gate driver circuit, said corresponding ones including control gates each of which is selected from different NAND type cell units which are associated with the same data transmission line.   
     
     
       5. The device according to claim 4, wherein said transfer gate means is connected to the selection gate of said switching transistor. 
     
     
       6. The device according to claim 5, wherein said control gate driver circuit comprises: a first driver section positioned on one side of said memory cell section; and   a second driver section positioned on the other side of said memory cell section.   
     
     
       7. The device according to claim 6, wherein said transfer gate means comprises: a first transfer gate section positioned on one side of said memory cell section and connected to said first driver section; and   a second transfer gate section positioned on the other side of said memory cell section and connected to said second driver section.   
     
     
       8. The device according to claim 7, further comprising: a first group of control gate output lines connected with said first transfer gate section and said first driver section; and   a second group of control gate output lines connected with said second transfer gate section and said first driver section.   
     
     
       9. A programmable read-only memory comprising: a semiconductive substrate;   bit lines insulatively formed above said substrate;   word lines formed above said substrate to intersect with said bit lines to have cross points therebetween;   rewritable memory cell transistors provided at the cross points, said memory cell transistors being grouped in NAND cell units each of which has a preselected number of memory cell transistors, said memory cell transistors comprising control gates and data storage layers;   switch means provided for cell units, for selectively connecting said sell units to the corresponding bit lines;   row decoder means connected to said word lines and said switch means, for selectively designating one or some of said word lines as selected lines by generating a predetermined level of voltage;   controller means for controlling said memory cell transistors so that each transistor is rendered conductive independently of the remaining cell transistors in a selected one of said NAND cell units,   said controller means having outputs and being associated with said NAND cell units so that mutually corresponding control gates of memory cell transistors, which belong to different NAND cell units associated with a certain bit line, are connected together to one of said outputs of said controller means; and   transfer gate means provided between said NAND cell units and said controller means, for selectively allowing a desired one of said mutually corresponding control gates to be connected to said controller means, while the other of said mutually corresponding control gates are electrically disconnected from said controller means.   
     
     
       10. The memory according to claim 9, further comprising: wiring lines provided in parallel with said bit lines, for connecting said NAND cell units with said controller means on said substrate.   
     
     
       11. The memory according to claim 10, wherein said controller means comprises a gate controller circuit which is positioned adjacent to said NAND cell units on said substrate. 
     
     
       12. The memory according to claim 10, wherein said NAND cell units are formed in a memory cell section on said substrate, and wherein said controller means comprises: a first gate controller circuit located on one side of said memory cell section; and   a second gate controller circuit located on the opposite side of said memory cell section on said substrate.   
     
     
       13. The memory according to claim 12, wherein said first gate controller circuit is associated with control gates of first memory cell transistors, while said second gate controller circuit is associated with control gates of second memory cell transistors in each NAND cell unit, said first and second memory cell transistors being arranged alternately in each NAND cell unit. 
     
     
       14. The memory according to claim 13, wherein said wiring lines comprise: a first group of wiring lines arranged on one side of said memory cell section and associated with said first gate controller circuit; and   a second group of wiring lines arranged on the opposite side of said memory cell section and associated with said second gate controller circuit.