Semiconductor device with bipolar and cmos transistors

Abstract

A semiconductor device having CMOS transistors and bipolar transistors is disclosed. A P-type high concentration buried region is formed in the surface region of the semiconductor substrate. An N-type epitaxial layer is formed on the buried region. The semiconductor device includes a second well region of a PMOS transistor that is formed by introducing an N-type impurity into a part of the epitaxial layer, and a first well region of a bipolar transistor that is formed without introducing the N-impurity, after the formation of the epitaxial layer.

What is claimed is: 
     
       1. A semiconductor device having a bipolar transistor and a CMOS transistor comprising: a semiconductor substrate of a first conductivity type;   a first high concentration buried region of the first conductivity type for preventing punch-through and soft error, said first high concentration buried region being formed on said semiconductor substrate;   second and third high concentration buried regions of a second conductivity type formed on said semiconductor substrate and located on either side of said first high concentration buried region;   a first well region of the second conductivity type, with a surface region, formed on said third high concentration buried region of the second conductivity type, a bipolar transistor being formed in the surface region of said first well region;   a second well region of the second conductivity type, with a surface region, formed on said second high concentration buried region of the second conductivity type, a first channel MOS transistor being formed in the surface region of said second well region, and an impurity concentration of said second well region being higher than an impurity concentration of said first well region; and   a third well region of the first conductivity type formed on said first high concentration buried region of the first conductivity type, a second channel MOS transistor being formed in the surface region of said third well region.   
     
     
       2. A semiconductor device according to claim 1, wherein said first well region is used while being doped with no impurity after formation of an epitaxial layer that is formed on said first, second and third high concentration buried regions. 
     
     
       3. A semiconductor device according to claim 2, wherein said epitaxial layer contains an N-type impurity at an impurity concentration in a range of 5×10 15  cm -3  to 2×10 16  cm -3 . 
     
     
       4. A semiconductor device according to claim 3, wherein said N-type impurity is phosphorus. 
     
     
       5. A semiconductor device according to claim 1, wherein said CMOS transistor includes a PMOS transistor having a gate length shorter than 0.8 μm. 
     
     
       6. A semiconductor device having a bipolar transistor and a CMOS transistor comprising: a semiconductor substrate of a first conductivity type;   a first high concentration buried region of the first conductivity type for preventing punch-through, said first high concentration buried region being formed on a portion of said semiconductor substrate to be used for a peripheral circuit;   a second high concentration buried region of the first conductivity type, for preventing soft error, formed in a portion of said semiconductor substrate to be used as a memory cell portion, an impurity concentration of said second high concentration buried region being higher than an impurity concentration of said first high concentration buried region;   third and fourth high concentration buried regions of a second conductivity type formed on said semiconductor substrate and located on either side of said first high concentration buried region;   a first well region of the second conductivity type, with a surface region, said first well region formed on said fourth high concentration buried region of the second conductivity type, a bipolar transistor being formed in the surface region of said first well region;   a second well region of the second conductivity type, with a surface region, said second well region formed on said third high concentration buried region, a first channel MOS transistor being formed in the surface region of said second well region, and an impurity concentration of said second well region being higher than an impurity concentration of said first well region; and   third and fourth well regions of the first conductivity type, each with a surface region, said third and fourth well regions formed, respectively, on said first and second high concentration buried regions, a second and a third channel MOS transistor respectively being formed in the surface region of each of said third and fourth well regions.   
     
     
       7. A semiconductor device according to claim 6, wherein said first well region is used while being doped with no impurity after formation of an epitaxial layer that is formed on said first, second, third and fourth high concentration buried regions. 
     
     
       8. A semiconductor device according to claim 7, wherein said epitaxial layer contains an N-type impurity at an impurity concentration in a range of 5×10 15  cm -3  to 2×10 16  cm -3 . 
     
     
       9. A semiconductor device according to claim 8, wherein said N-type impurity is phosphorus. 
     
     
       10. A semiconductor device according to claim 6, wherein said second high concentration buried region is isolated from a fifth high concentration buried region of the first conductivity type which is located between said second and fourth high concentration regions and is separated from said second high concentration buried region of the second conductivity type by at least 2 μm. 
     
     
       11. A semiconductor device according to claim 6, wherein said CMOS transistor includes a PMOS transistor having a gate length shorter than 0.8 μm.