Parity and error correction coding on integrated circuit addresses

Abstract

A more secure method for selecting and addressing individual integrated circuit chips and memory locations, registers or input/output ports within the chips includes supplying the chips with address information including address checking information, checking the address information actually received in the chip by using an address checking circuit in the integrated circuit, and inhibiting use of the address information in the chip when the address checking circuit indicates an erroneous address. By inhibiting the use of erroneous address information, state information stored in the integrated circuit is not lost. The integrated circuit sends a fault signal requesting retransmission of the address information for recovery from the address fault. Preferably the address checking information is an error detecting and correcting code for correcting single-bit errors and detecting double-bit errors. Then the integrated circuit functions properly with one defective address input.

We claim: 
     
       1. A method of addressing a memory integrated circuit during a memory write operation, said memory integrated circuit having a plurality of addressable memory locations, each of said addressable memory locations having a respective one of a plurality of preassigned address, said method comprising the steps of: a) encoding one of said preassigned addresses according to an error detecting code to provide address information, said error detecting code permitting detection of error introduced into said address information during transmission of said address information;   b) transmitting data and said address information from a second circuit to said memory integrated circuit;   c) checking the address information actually received by said memory integrated circuit by using an address checking circuit in said memory integrated circuit to determine whether error was introduced into said address information during the transmission of the address information to said memory integrated circuit, and when said checking determines that error was introduced into said address information during said transmission of the address information to said memory integrated circuit, (i) inhibiting writing of said data to one of said addressable memory locations addressed by said address information actually received by said memory integrated circuit, and   (ii) transmitting a fault signal from the memory integrated circuit to said second circuit to signal a failure of said memory write operation to be completed.     
     
     
       2. The method as claimed in claim 1, further comprising the step of said second circuit retransmitting said address information to said memory integrated circuit in response to said fault signal. 
     
     
       3. The method as claimed in claim 1, wherein said second circuit includes a data processing unit, and said method further comprises the step of interrupting said data processing unit to perform a predefined addressing fault handling routine in response to said fault signal. 
     
     
       4. A method of addressing a memory integrated circuit during a memory read operation, said memory integrated circuit having a plurality of addressable memory locations, each of said addressable memory locations having a respective one of a plurality of preassigned addresses, said method comprising the steps of: a) encoding one of said preassigned addresses according to an error detecting code to provide address information, said error detecting code permitting detection of error introduced into said address information during transmission of said address information;   b) transmitting said address information form a second circuit to said memory integrated circuit;   c) checking the address information actually received by said memory integrated circuit by using an address checking circuit in said memory integrated circuit to determine whether error was introduced into said address information during the transmission of the address information to said memory integrated circuit, and when said checking determines that error was introduced into said address information during said transmission of the address information to said memory integrated circuit, transmitting a fault signal from the memory integrated circuit to said second circuit to signal the occurrence of said error, and retransmitting said address information from said second circuit to said memory integrated circuit in response to said fault signal.   
     
     
       5. The method as claimed in claim 4, wherein said second circuit includes a data processing unit, and said method comprises the step of interrupting said data processing unit to perform a predefined addressing fault handling routine in response to said fault signal. 
     
     
       6. The method as claimed in claim 5, wherein said predefined addressing fault handling routine halts the data processing unit and logs the occurrence of the fault when the fault signal continues a predetermined number of times. 
     
     
       7. A method of addressing an integrated circuit during a write operation, said integrated circuit having a plurality of addressable registers, each of said addressable registers having a respective one of a plurality of preassigned address, said method comprising the steps of: encoding one of said preassigned addresses according to an error detecting code to provide address information, said error detecting code permitting detection of error introduced into said address information during transmission of said address information;   b) transmitting data and said address information from a second circuit to said integrated circuit;   c) checking the address information actually received by said integrated circuit by using an address checking circuit in said integrated circuit to determine whether error was introduced into said address information during the transmission of the address information to said integrated circuit, and when said checking determines that error was introduced into said address information during said transmission of the address information to said integrated circuit, (i) inhibiting writing of said data to one of said registers addressed by said address information actually received by said integrated circuit, and   (ii) transmitting a fault signal from the integrated circuit to said second circuit to signal a failure of said write operation to be completed.     
     
     
       8. The method as claimed in claim 7, further comprising the step of said second circuit retransmitting said address information to said integrated circuit in response to said fault signal. 
     
     
       9. The method as claimed in claim 7, wherein said second circuit includes a data processing unit, and said method comprises the step of interrupting said data processing unit to perform a predefined addressing fault handling routine in response to said fault signal. 
     
     
       10. A method of addressing a memory integrated circuit during a memory write operation, said memory integrated circuit having a plurality of addressable memory locations, each of said addressable memory locations having a respective one of a plurality of preassigned address, said method comprising the steps of: a) encoding one of said preassigned addresses according to an error detecting and correcting code to provide address information, said error detecting and correcting code permitting correction of correctable error introduced into said address information during transmission of said address information, and permitting detection of uncorrectable error introduced into said address information during transmission of said address information;   b) transmitting data and said address information from a second circuit to said memory integrated circuit;   c) checking the address information actually received by said memory integrated circuit by using an address checking and correcting circuit in said memory integrated circuit to correct correctable error introduced into said address information during the transmission of the address information to said memory integrated circuit, and to determine whether uncorrectable error was introduced into said address information during the transmission of the address information to said memory integrated circuit, and when said checking determines that uncorrectable error was introduced into said address information during said transmission of the address information to said memory integrated circuit, (i) inhibiting writing of said data to one of said addressable memory locations addressed by said address information actually received by said memory integrated circuit, and   (ii) transmitting a fault signal from said memory integrated circuit to said second circuit to signal a failure of said memory write operation to be completed.     
     
     
       11. The method as claimed in claim 10, further comprising the step of said second circuit retransmitting said address information to said memory integrated circuit in response to said fault signal. 
     
     
       12. The method as claimed in claim 10, wherein said second circuit includes a data processing unit, and said method comprises the step of interrupting said data processing unit to perform a predefined addressing fault handling routine in response to said fault signal. 
     
     
       13. The method as claimed in claim 10, further comprising the step of comparing a portion of the corrected address information to chip select information prestored in the memory integrated circuit to determine whether said corrected address addresses any of the addressable memory locations in said memory integrated circuit, and when said step of comparing indicates that said corrected address fails to address any of the addressable memory locations in said memory integrated circuit, inhibiting the writing of said data into any of said addressable memory locations. 
     
     
       14. The method as claimed in claim 10, wherein said step (b) of transmitting data and said address information includes transmitting said data over a data bus to said memory integrated circuit, transmitting a first portion of said address information over an address bus to said memory integrated circuit, and transmitting a second portion of said address information over said data bus to said memory integrated circuit. 
     
     
       15. The method as claimed in claim 14, wherein said step (b) of transmitting data and said address information includes transmitting a row address strobe and a column address strobe to said integrated circuit, transmitting row address information over said address bus and transmitting additional address information over said data bus during a first portion of a cycle of said row address strobe, and transmitting column address information over said address bus and said data over said data bus during a second portion of said cycle of said row address strobe. 
     
     
       16. A memory integrated circuit comprising terminals for connection to an address bus and a data bus, a plurality of addressable memory locations each having a respective one of a plurality of predetermined addresses, and means for transferring data between said data bus and each of said addressable memory locations when said address information received on said terminals indicates the predetermined address of said each of said addressable memory locations, wherein said memory integrated circuit further comprises: address checking means, connected to a multiplicity of said terminals and responsive to error detection coding in said address information, for detecting error in said address information,   fault signal transmitting means, connected to said address checking means and at least one of said terminals, for transmitting a fault signal from said memory integrated circuit when said address checking means detects error in said address information, and   inhibiting means, connected to said address checking means, for inhibiting writing of said data from said terminals to any of said addressable memory locations when said address checking means detects error in said address information.   
     
     
       17. The memory integrated circuit as claimed in claim 16, wherein said means for transmitting a fault signal includes a pull-down transistor for sinking current from said one of said terminals. 
     
     
       18. A memory integrated circuit comprising terminals for connection to an address bus and a data bus, a plurality of addressable memory locations each having a respective one of a plurality of predetermined addresses, and means for transferring data between said data bus and each of said addressable memory locations when said address information received on said terminals indicates the predetermined address of said each of said addressable memory locations; wherein said memory integrated circuit further comprises: address checking and correcting means, connected to a multiplicity of said terminals and responsive to error detecting and correcting coding in said address information, for correcting correctable errors in said address information to provide corrected address information, and for detecting uncorrectable errors in said address information,   fault signal transmitting means, connected to said address checking and correcting means and at least one of said terminals, for transmitting a fault signal from said memory integrated circuit when said address checking means detects uncorrectable error in said address information, and   inhibiting means, connected to said address checking and correcting means, for inhibiting writing of said data from said terminals to any of said addressable memory locations when said address checking and correcting means detects uncorrectable error in said address information.   
     
     
       19. The memory integrated circuit as claimed in claim 18, wherein said means for transmitting a fault signal includes a pull-down transistor for sinking current from said one of said terminals. 
     
     
       20. The memory integrated circuit as claimed in claim 18, further comprising comparing means, connected to said address checking and correcting means, for comparing a portion of the corrected address information to chip select information prestored in said memory integrated circuit to determine whether said corrected address information fails to indicate any of the addressable memory locations in said memory integrated circuit, and inhibiting writing of said data into any of the addressable memory locations when said corrected address fails to address any of said addressable memory locations. 
     
     
       21. The memory integrated circuit as claimed in claim 20, further comprising an electrically programmable memory providing said programmed address information. 
     
     
       22. The memory integrated circuit as claimed in claim 18, wherein said error checking and correcting means includes a syndrome generator and a syndrome decoder for indicating erroneous bits in said address information. 
     
     
       23. The memory integrated circuit as claimed in claim 18, further comprising de-multiplexing means connected to a plurality of said terminals for receiving a portion of said data and a portion of said address information from the same ones of said plurality of said terminals.