Semiconductor device having stacked lead structure

Abstract

Disclosed is a resin-molded type semiconductor device having a thin package while avoiding short-circuit of wires with a common inner lead. In the construction thereof, a common inner lead constituted by a thin metal sheet is fixed onto a circuit-forming surface of a rectangular semiconductor chip substantially in parallel with longer sides of the chip and substantially in a central region of the chip, and a plurality of inner leads for signals, which are in the form of a frame, are stacked and fixed onto the common inner lead; then these components are molded with resin.

What is claimed is: 
     
       1. A semiconductor device comprising: a semiconductor chip having on a principal surface thereof a plurality of external terminals;   leads comprising first leads for providing voltages and second leads for providing signals, each of said first and second leads comprising an inner lead portion having a first part and a second part and an outer lead portion connected to said second part and extending in a direction away from said first part;   a metal layer interposed between the principal surface of the semiconductor chip and the first part of said inner lead portion of the leads, said first part of said inner lead portion of the leads overlying said metal layer, the metal layer being connected electrically to the first leads; and   a plurality of wires comprising first wires and second wires, said first wires electrically connecting the first part of said inner lead portion of the second leads with a first group of said plurality of the external terminals, said second wires electrically connecting said metal layer with a second group of said plurality of the external terminals.   
     
     
       2. A semiconductor device according to claim 1, wherein the first part of the inner lead portion of the leads is stacked upon said metal layer. 
     
     
       3. A semiconductor device according to claim 1, wherein the semiconductor chip is substantially rectangular, and has integrated circuits on the principal surface thereof. 
     
     
       4. A semiconductor device according to claim 1, further comprising a molded member covering said semiconductor chip, said inner lead portions, said metal layer and said plurality of wires. 
     
     
       5. A semiconductor device according to claim 4, wherein said molded member is made of a resin material, whereby the semiconductor device is a resin-molded semiconductor device. 
     
     
       6. A semiconductor device according to claim 5, wherein the semiconductor chip is substantially rectangular, and wherein the second part of said inner lead portion of each lead is arranged on shorter sides of the semiconductor chip. 
     
     
       7. A semiconductor device according to claim 4, further comprising an adhesive layer, for bonding, between the principal surface of the semiconductor chip and said metal layer. 
     
     
       8. A semiconductor device according to claim 7, further comprising an insulating base interposed between said metal layer and the first part of said inner lead portion of the leads. 
     
     
       9. A semiconductor device according to claim 8, further comprising adhesive layers respectively on surfaces of the insulating base adjacent the metal layer and the first part of said inner lead portion of the leads. 
     
     
       10. A semiconductor device according to claim 4, wherein the semiconductor chip is substantially rectangular, and wherein said external terminals are arranged substantially in parallel with longer sides of the semiconductor chip and in a central region of the chip. 
     
     
       11. A semiconductor device according to claim 10, wherein said metal layer is formed in a continuous manner along said external terminals. 
     
     
       12. A semiconductor device according to claim 4, further comprising connecting wires for electrical connection between said first leads and said metal layer. 
     
     
       13. A semiconductor device according to claim 12, wherein said first leads and said metal layer are electrically connected at a plurality of points. 
     
     
       14. A semiconductor device according to claim 4, wherein said metal layer is constituted by an iron-nickel alloy sheet. 
     
     
       15. A semiconductor device according to claim 4, wherein the semiconductor chip is substantially rectangular, and wherein the second part of said inner lead portion of each lead is arranged on longer sides of the semiconductor chip. 
     
     
       16. A semiconductor device according to claim 1, wherein portions of the metal layer are exposed between adjacent first parts of said inner lead portions of the leads, and wherein said second wires electrically connect the exposed metal layer portions and the second group of said plurality of the external terminals. 
     
     
       17. A semiconductor device according to claim 1, wherein the second wires have two ends, and wherein one end of each of the second wires is connected to the metal layer, and the other end of each of the second wires is connected to the second group of the external terminals. 
     
     
       18. A semiconductor device according to claim 1, wherein the metal layer is a metal foil. 
     
     
       19. A semiconductor device according to claim 1, wherein the first wires do not cross over the metal layer. 
     
     
       20. A semiconductor device according to claim 1, wherein an area of the principal surface of the semiconductor chip, between the external terminals and an area of the principal surface having the leads thereover, is free of a bus bar inner lead thereover. 
     
     
       21. A semiconductor device according to claim 1, wherein said semiconductor chip has a memory cell array and peripheral circuitry. 
     
     
       22. A semiconductor device according to claim 1, wherein said semiconductor chip is substantially rectangular, and wherein points where the first wires are electrically connected to the first part of the inner lead portion of the second leads are arranged substantially in a line which is in a direction parallel with longer sides of the semiconductor chip. 
     
     
       23. A semiconductor device according to claim 1, wherein said metal layer is smaller than the semiconductor chip. 
     
     
       24. A semiconductor device comprising: a semiconductor chip having on a principal surface thereof a plurality of external terminals;   leads comprising first leads for providing voltages and second leads for providing signals, each of said first and second leads comprising an inner lead portion having a first part and a second part and an outer lead portion connected to said second part and extending in a direction away from said first part;   a metal layer stacked on the first part of said inner lead portion of the leads, overlying said first part of said inner lead portion of the leads, and connected electrically to said first leads; and   a plurality of wires comprising first wires and second wires, said first wires electrically connecting the first part of said inner lead portion of the second leads with a first group of the external terminals, said second wires electrically connecting said metal layer with a second group of the external terminals.   
     
     
       25. A semiconductor device according to claim 24, wherein the semiconductor chip is substantially rectangular, and has integrated circuits on the principal surface thereof. 
     
     
       26. A semiconductor device according to claim 24, further comprising a molded member covering said semiconductor chip, said inner lead portions, said metal layer and said plurality of wires. 
     
     
       27. A semiconductor device according to claim 26, wherein said molded member is made of a resin material, whereby the semiconductor device is a resin-molded semiconductor device. 
     
     
       28. A semiconductor device according to claim 26, further comprising an insulating base interposed between the principal surface of the semiconductor chip and the first part of said inner lead portion of the leads. 
     
     
       29. A semiconductor device according to claim 28, further comprising adhesive layers respectively on surfaces of the insulating base adjacent the principal surface of the semiconductor chip and the first part of said inner lead portion of the leads. 
     
     
       30. A semiconductor device according to claim 28, further comprising an adhesive layer for bonding, between the first part of said inner lead portion of the leads and said metal layer. 
     
     
       31. A semiconductor device according to claim 26, wherein the semiconductor chip is substantially rectangular, and wherein said external terminals are arranged substantially in parallel with longer sides of the semiconductor chip and in a central region of the chip. 
     
     
       32. A semiconductor device according to claim 31, wherein said metal layer is formed in a continuous manner along said external terminals. 
     
     
       33. A semiconductor device according to claim 26, further comprising wires for electrical connection between said first leads and said metal layer. 
     
     
       34. A semiconductor device according to claim 33, wherein said first leads and said metal layer are electrically connected at a plurality of points. 
     
     
       35. A semiconductor device according to claim 26, wherein said metal layer is constituted by an iron-nickel alloy sheet. 
     
     
       36. A semiconductor device according to claim 26, wherein the semiconductor chip is substantially rectangular, and wherein the second part of said inner lead portion of each lead is arranged on a longer side of the semiconductor chip. 
     
     
       37. A semiconductor device according to claim 26, wherein the semiconductor chip is substantially rectangular, and wherein the second part of said inner lead portion of each lead is arranged on a shorter side of the semiconductor chip. 
     
     
       38. A semiconductor device according to claim 24, wherein said semiconductor chip has a memory cell array and peripheral circuitry. 
     
     
       39. A semiconductor device according to claim 24, wherein said semiconductor chip is substantially rectangular, and wherein points where the first wires are electrically connected to the first part of the inner lead portion of the second leads are arranged substantially in a line which is in a direction parallel with longer sides of the semiconductor chip. 
     
     
       40. A semiconductor device according to claim 24, wherein said metal layer is smaller than the semiconductor chip. 
     
     
       41. A semiconductor device according to claim 24, wherein an area of the principal surface of the semiconductor chip, between the external terminals and an area of the principal surface having the leads thereover, is free of a bus bar inner lead thereover. 
     
     
       42. A semiconductor device according to claim 24, wherein said second wires are connected to the metal layer at locations directly over said first part of the inner lead portion of the second leads. 
     
     
       43. A semiconductor device according to claim 24, wherein the first part of the inner lead portion of the second leads has exposed structure that extends, in a direction toward the external terminals, beyond the metal layer, and wherein the first wires are connected to the exposed structure of the first part of the inner lead portion of the second leads. 
     
     
       44. A semiconductor device according to claim 24, wherein the second wires have two ends, and wherein one end of each of the second wires is connected to the metal layer, and the other end of each of the second wires is connected to the second group of the external terminals.