US5256594AExpiredUtility

Masking technique for depositing gallium arsenide on silicon

86
Assignee: INTEL CORPPriority: Jun 16, 1989Filed: Jun 16, 1989Granted: Oct 26, 1993
Est. expiryJun 16, 2009(expired)· nominal 20-yr term from priority
Inventors:Albert WuShinji NozakiThomas GeorgeSandra S. LeeMasayoshi Umeno
H10P 14/3421H10P 14/3248H10P 14/3238H10P 14/3221H10P 14/2905H10P 14/271H10P 14/24C23C 16/042C23C 14/042Y10S438/933Y10S438/916
86
PatentIndex Score
82
Cited by
29
References
29
Claims

Abstract

A process for forming GaAs on a silicon substrate with very low levels of unintended silicon doping. First, a dielectric layer of silicon dioxide, silicon nitride, or both is grown or deposited on the substrate. Next, a window is opened in the dielectric layer exposing the silicon substrate in the regions in which the GaAs is to be formed. The GaAs layer is then formed on the substrate using conventional techniques with the gas phase transfer of silicon contamination from the edges and back of the silicon substrate to the GaAs region inhibited by the dielectric layer or layers.

Claims

exact text as granted — not AI-modified
We claim: 
     
       1. A process for the formation of gallium arsenide on a silicon substrate in which silicon contamination of the GaAs layer is inhibited comprising the steps of: depositing a dielectric layer on said substrate to substantially cover the top, bottom and edge of said substrate;   exposing a predetermined region of said substrate by removing portions of said dielectric layer;   forming a gallium arsenide layer on said predetermined region of said substrate.   
     
     
       2. The process as described in claim 1 wherein said dielectric layer is comprised of silicon dioxide having a thickness of approximately 200-10,000 angstroms. 
     
     
       3. The process as described in claim 1 wherein said dielectric layer is comprised of silicon nitride having a thickness of approximately 200-10,000 angstroms. 
     
     
       4. The process as described in claim 1 wherein said gallium arsenide layer is formed by metalorganic chemical vapor deposition. 
     
     
       5. The process as described in claim 2 wherein said gallium arsenide layer is formed by metalorganic chemical vapor deposition. 
     
     
       6. The process as described in claim 3 wherein said gallium arsenide layer is formed by metalorganic chemical vapor deposition. 
     
     
       7. The process as described in claim 1 wherein said gallium arsenide layer is formed by metalorganic vapor phase epitaxy. 
     
     
       8. The process as described in claim 2 wherein said gallium arsenide layer is formed by metalorganic vapor phase epitaxy. 
     
     
       9. The process as described in claim 3 wherein said gallium arsenide layer is formed by metalorganic vapor phase epitaxy. 
     
     
       10. The process as described in claim 1 wherein said gallium arsenide layer is formed by molecular beam epitaxy. 
     
     
       11. The process as described in claim 2 wherein said gallium arsenide layer is formed by molecular beam epitaxy. 
     
     
       12. The process as described in claim 3 wherein said gallium arsenide layer is formed by molecular beam epitaxy. 
     
     
       13. A process for the formation of gallium arsenide on a silicon substrate in which silicon contamination of the GaAs layer is inhibited comprising the steps of: depositing a first dielectric layer on the top, bottom and edge of said substrate;   depositing a second dielectric layer on said first dielectric layer;   exposing a predetermined region of said substrate by removing portions of said first and said second dielectric layers;   forming a gallium arsenide layer on said predetermined region.   
     
     
       14. The process as described in claim 13 wherein said first dielectric layer is comprised of silicon dioxide having a thickness of approximately 200-10,000 angstroms, and said second dielectric layer is comprised of silicon nitride having a thickness of approximately 500-10,000 angstroms. 
     
     
       15. The process as described in claim 13 wherein said first dielectric layer is comprised of silicon nitride having a thickness of approximately 500-10,000 angstroms, and said second dielectric layer is comprised of silicon dioxide having a thickness of approximately 200-10,000 angstroms. 
     
     
       16. The process as described in claim 13 wherein said gallium arsenide layer is formed by metalorganic chemical vapor deposition. 
     
     
       17. The process as described in claim 14 wherein said gallium arsenide layer is formed by metalorganic chemical vapor deposition. 
     
     
       18. The process as described in claim 15 wherein said gallium arsenide layer is formed by metalorganic chemical vapor deposition. 
     
     
       19. The process as described in claim 13 wherein said gallium arsenide layer is formed by metalorganic vapor phase epitaxy. 
     
     
       20. The process as described in claim 14 wherein said gallium arsenide layer is formed by metalorganic vapor phase epitaxy. 
     
     
       21. The process as described in claim 15 wherein said gallium arsenide layer is formed by metalorganic vapor phase epitaxy. 
     
     
       22. The process as described in claim 13 wherein said gallium arsenide layer is formed by molecular beam epitaxy. 
     
     
       23. The process as described in claim 14 wherein said gallium arsenide layer is formed by molecular beam epitaxy. 
     
     
       24. The process as described in claim 15 wherein said gallium arsenide layer is formed by molecular beam epitaxy. 
     
     
       25. A process for the formation of gallium arsenide on a silicon substrate in which silicon contamination of the GaAs layer is inhibited comprising the steps of: depositing a first silicon dioxide layer of approximately 200-2000 angstroms thickness on said substrate;   depositing a silicon nitride layer of approximately 500-2000 angstroms thickness on said first silicon dioxide layer;   removing a portion of said silicon nitride layer such that a predetermined region of said silicon nitride layer remains atop said first silicon dioxide layer;   depositing a second silicon dioxide layer on said first silicon dioxide layer;   removing said predetermined region of said silicon nitride layer to expose an underlying predetermined region of said first silicon dioxide layer;   removing said underlying predetermined region of said first silicon dioxide layer to expose a portion of said silicon substrate;   forming a gallium arsenide layer on said exposed portion of said silicon substrate.   
     
     
       26. The process as described in claim 25 wherein said gallium arsenide layer is formed by metalorganic chemical vapor deposition. 
     
     
       27. The process as described in claim 25 wherein said gallium arsenide layer is formed by metalorganic vapor phase epitaxy. 
     
     
       28. The process as described in claim 25 wherein said gallium arsenide layer is formed by molecular beam epitaxy. 
     
     
       29. The process as described in claim 25 wherein said first silicon dioxide layer is deposited on the top, bottom and edge of said substrate.

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