Semiconductor memory device divided into blocks and operable to read and write data through different data lines and operation method of the same

Abstract

In a DRAM of separated I/O type, column selecting lines for reading data and column selecting lines for writing data are provided independently from each other. An addition circuit is provided corresponding to each memory cell array block for precharging, when that memory cell array is not selected, a read line pair corresponding that memory cell array block to the same potential Vb1 as that of the bit lines equalized by an equalizer circuit. Both in data reading and writing operations, current does not flow between any equalizer circuit and the write data line pair provided corresponding to each unselected memory cell array block in spite of the fact that a transistor for write selection is not provided in each bit line pair.

What is claimed is: 
     
       1. A semiconductor memory device comprising: a plurality of blocks each including a plurality of memory cells disposed in a plurality of rows and a plurality of columns, and a plurality of bit lines provided corresponding to said plurality of columns;   first selecting means for selecting any of said plurality of bit lines in each of said plurality of blocks in a data writing operation;   second selecting means for selecting any of said plurality of bit lines in each of said plurality of blocks in a data reading operation;   block selecting means for selecting any of said plurality of blocks;   a plurality of write data bus means provided corresponding to said plurality of blocks each receiving write data;   a plurality of connecting means provided corresponding to said plurality of blocks each for electrically connecting said bit line selected by said first selecting means in the corresponding block to the corresponding write data bus means;   a plurality of read data bus means provided corresponding to said plurality of blocks each for externally transmitting read data;   a plurality of transmitting means provided corresponding to said plurality of blocks each for transmitting potential variation in said bit line selected by said second selecting means in the corresponding block to the corresponding read data bus means;   a plurality of read amplifier means provided corresponding to said plurality of blocks each for amplifying said potential variation transmitted by the corresponding transmitting means;   a plurality of equalizer means provided corresponding to said plurality of blocks each for equalizing all of said bit lines in the corresponding block to a predetermined potential Vb1, when the corresponding block is not selected by said block selecting means; and   a plurality of precharging means provided corresponding to said plurality of blocks each for precharging the corresponding write data bus means to said predetermined potential, when the corresponding block is not selected by said block selecting means in data writing operation.   
     
     
       2. The semiconductor memory device according to claim 1, further comprising common write data bus means provided commonly corresponding to said plurality of blocks for receiving said write data externally applied thereto, wherein each of said plurality of precharging means includes   first switching means for electrically connecting the corresponding write data bus means to said common write data bus means for a period in which the corresponding block is selected by said block selecting means in said data writing operation, and for electrically isolating the corresponding write data bus means from said common write data bus means in said data reading operation and for other periods in said data writing operation; and   second switching means for electrically coupling the corresponding write data bus means to said predetermined potential in said data reading operation and for a period in which the corresponding block is not selected by said block selecting means in said data writing operation, and for electrically isolating the corresponding data bus means from said predetermined potential for a period in which the corresponding block is selected by said block selecting means in said data writing operation.   
     
     
       3. The semiconductor memory device according to claim 2, wherein each of said first switching means includes a first field effect semiconductor element having a first conductive terminal connected to the corresponding write data bus means, a second conductive terminal connected to said common write data bus means, and a control terminal for receiving a first control signal; and each of said second switching means includes a second field effect semiconductor element having a first conductive terminal connected to the corresponding write data bus means, a second conductive terminal for receiving said predetermined potential, and a control terminal receiving a second control signal having a logical level complementary to said first control signal.   
     
     
       4. The semiconductor memory device according to claim 3, wherein said block selecting means supplies, to each of said plurality of blocks, a signal of a first logical level indicating selection of that block or a signal of a second level indicating non-selection of that block as said first control signal in response to a data write designating signal designating data write mode in the semiconductor device and to an address signal, and supplies as said second control signal, a signal of said second logical level to each of said plurality of blocks in response to a signal designating a mode other than said data write mode, regardless of said address signal.   
     
     
       5. The semiconductor memory device according to claim 4, wherein each of said plurality of connecting means includes a plurality of third switching means connected between said plurality of bit lines in the corresponding block and the corresponding write data bus means, respectively, and controlled independently from each other by said first selecting means; and each of said plurality of transmitting means includes a plurality of fourth switching means, connected between said plurality of bit lines in the corresponding block and the corresponding read data bus means, respectively, and controlled independently from each other by said second selecting means.   
     
     
       6. The semiconductor memory device according to claim 5, wherein said second selecting means includes first decoding means for decoding said address signal to generate a third control signal for turning on only one of said fourth switching means in each of said plurality of blocks and turning off all other fourth switching means in each of said plurality of blocks; and said first selecting means includes second decoding means responsive to said third control signal generated by said first decoding means and to said data write instructing signal for generating a fourth control signal, which turns on only one of said third switching means in each of said plurality of blocks and turns off all other third switching means in the data writing operation, and turns off all of said third switching means in each of said plurality of blocks in said data reading operation.   
     
     
       7. The semiconductor memory device according to claim 6, wherein said third control signal includes a plurality of transmission control signals for controlling said plurality of third switching means included in each of said plurality of blocks, respectively; said plurality of transmission control signals are commonly applied to said plurality of blocks;   said fourth control signal includes a plurality of connection control signals for controlling said plurality of fourth switching means included in each of said plurality of blocks, respectively; and   said plurality of connection control signals are commonly applied to said plurality of blocks.   
     
     
       8. The semiconductor memory device according to claim 7, wherein said second decoding means includes a plurality of logic circuit means provided corresponding to said plurality of transmission of control signals, each for generating a logical product signal of the corresponding transmission control signal and said data write instructing signal; and output signals of said plurality of said logic circuit means are used as said plurality of connection control signals, respectively.   
     
     
       9. The semiconductor memory device according to claim 1, wherein said predetermined potential is an intermediate potential between a power supply potential and a ground potential. 
     
     
       10. The semiconductor memory device according to claim 1, wherein each of said memory cells is a dynamic memory cell. 
     
     
       11. A semiconductor memory device comprising: a plurality of blocks each including a plurality of dynamic memory cells disposed in a plurality of rows and a plurality of columns, and a plurality of bit line pairs provided correspondingly to said plurality of columns;   first selecting means for selecting any of said plurality of bit line pairs in each of said blocks in a data writing operation;   second selecting means for selecting any of said plurality of bit line pairs in each of said plurality of blocks in a data reading operation;   block selecting means for selecting any of said plurality of blocks; and   a plurality of write data line pairs provided corresponding to said plurality of blocks each for receiving write data; wherein   each of said bit line pairs includes first and second bit lines, and   each of said write data line pairs includes first and second write data lines;   said semiconductor memory device further comprising;   a plurality of connecting means which are provided corresponding to said plurality of blocks, each for electrically connecting said first and second bit lines included in the bit line pair selected by said first selecting means to said first and second write data lines included in the corresponding write data line pair, in the corresponding block,   a plurality of read data line pairs provided corresponding to said plurality of blocks, each for externally transmitting read data,   each of said plurality of read data line pairs including first and second read data lines;   a plurality of transmitting means provided corresponding to said plurality of blocks, each for transmitting potential variation in said first and second bit lines included in the bit line pair selected by said second selecting means to said first and second read data lines included in the corresponding read data line pair, in the corresponding block;   a plurality of read amplifier means provided corresponding to said plurality of blocks, each for amplifying potential difference between said first and second read data lines included in the corresponding read data line pair;   a plurality of equalizer means provided corresponding to said plurality of blocks each for equalizing said first and second bit lines included in each of said plurality of bit line pairs in the corresponding block, to a predetermined potential, when the corresponding block is not selected by said block selecting means; and   a plurality of precharging means provided corresponding to said plurality of blocks, each for precharging said first and second write data lines included in the corresponding write data line pair, to said predetermined potential, when the corresponding block is not selected by said block selecting means in the data writing operation.   
     
     
       12. The semiconductor memory device according to claim 11, further comprising a common write data line pair provided commonly corresponding to said plurality of blocks, receiving said write data externally applied thereto, wherein   each of said precharging means includes:   first switching means for electrically connecting the corresponding write data line pair to said common write data line pair for a period in which the corresponding block is selected by said block selecting means in said data writing operation, and for electrically isolating the corresponding data line pair from said common write data line pair in said data reading operation and for other periods in said data writing operation; and   second switching means for electrically coupling the corresponding write data line pair to said predetermined potential in said data reading operation and for a period in which the corresponding block is not selected by said block selecting means in said data writing operation, and for electrically isolating the corresponding data line pair from said predetermined potential for a period in which the corresponding block is selected by said block selecting means in said data writing operation.   
     
     
       13. A semiconductor memory device comprising: a plurality of blocks each including a plurality of memory cells disposed in a plurality of rows and a plurality of columns, and a plurality of bit lines provided corresponding to said plurality of columns;   first selecting means for selecting any of said plurality of bit lines in each of said plurality of blocks in a data writing operation;   second selecting means for selecting any of said plurality of bit lines in each of said plurality of blocks in a data reading operation;   block selecting means for selecting any of said plurality of blocks;   a plurality of write data bus means provided corresponding to said plurality of blocks each receiving write data;   a plurality of connecting means provided corresponding to said plurality of blocks each for electrically connecting said bit line selected by said first selecting means in the corresponding block to the corresponding write data bus means;   a plurality of read data bus means provided corresponding to said plurality of blocks each for externally transmitting read data;   a plurality of transmitting means provided corresponding to said plurality of blocks each for transmitting potential variation in said bit line selected by said second selecting means in the corresponding block to the corresponding read data bus means;   a plurality of read amplifier means provided corresponding to said plurality of blocks each for amplifying said potential variation transmitted by the corresponding transmitting means;   a plurality of equalizer means provided corresponding to said plurality of blocks each for equalizing all of said bit lines in the corresponding block to a predetermined potential Vb1, when the corresponding block is not selected by said block selecting means; and   a plurality of precharging means provided corresponding to said plurality of blocks each for precharging the corresponding write data bus means to said predetermined potential, when the corresponding block is not selected by said block selecting means in data writing operation,   said first selecting means being responsive to a selected output from said second selecting means and a control signal instructing said data writing for generating a signal selecting any one of said plurality of bit lines.   
     
     
       14. An operation method of a semiconductor memory device including a plurality of blocks, each including memory cells disposed in a plurality of rows and a plurality of columns, a plurality of bit lines provided corresponding to said plurality of columns, a write data bus for receiving write data, and a read data bus for externally transmitting read data, said method comprising the steps of: selecting any of said plurality of bit lines in each of said plurality of blocks in a data writing operation;   selecting any of said plurality of bit lines in each of said plurality of blocks in a data reading operation;   selecting any of said plurality of blocks;   electrically connecting the selected bit line to the corresponding write data bus in each of said plurality of blocks;   transmitting potential variation in the selected bit line to the corresponding read data bus in each of said plurality of blocks;   electrically amplifying said transmitted potential variation;   equalizing all of said bit lines in the unselected block to a predetermined potential; and   precharging said write data bus in the unselected block to said predetermined potential.