Method of fabricating a flash memory cell

Abstract

A flash memory cell includes the usual thermal oxide layer deposited above the substrate including the source and the drain. On the thermal oxide layer, a silicon rich oxide layer is formed. Above the silicon rich oxide layer a gate structure is formed of layer of polysilicon separated by an intermediate dielectric layer. The lower polysilicon layer commences as an initial portion of the layer of small grain size followed by either amorphous or large grain size material.

Having thus described the invention, what is claimed as new and desirable to be secured by Letters Patent is as follows: 
     
       1. A method of forming a self-aligned flash MOS field effect transistor structure on a silicon semiconductor substrate having an upper surface, a) forming a source region and a drain region in said substrate on said upper surface,   b) forming a tunnel oxide structure over the surface of said substrate including the surface of said source and said drain regions,   c) said tunnel oxide structure including a thermal oxide layer formed on the surface said substrate and a film of silicon rich oxide deposited upon said thermal oxide layer, and   e) depositing a gate structure composed of a stack upon said silicon rich oxide film, said stack comprising a first polysilicon layer, a dielectric layer deposited upon said polysilicon layer and a second polysilicon layer deposited upon said dielectric layer.   
     
     
       2. A method in accordance with claim 1 wherein said silicon rich oxide is deposited by chemical vapor deposition. 
     
     
       3. A method in accordance with claim 1 wherein said first polysilicon layer includes a lower portion composed of relatively smaller grain size crystals, and an upper portion composed of amorphous polysilicon. 
     
     
       4. A method in accordance with claim 3 wherein said silicon rich oxide is deposited by chemical vapor deposition. 
     
     
       5. A method in accordance with claim 1 wherein said first polysilicon layer includes a lower portion composed of relatively smaller grain size crystals, and an upper portion composed of a structure composed of larger grain size crystals. 
     
     
       6. A method in accordance with claim 5 wherein said silicon rich oxide is deposited by chemical vapor deposition. 
     
     
       7. A method in accordance with claim 5 wherein the thickness of said silicon rich oxide layer is within the range between about 50 Å and about 200 Å and the thickness of said thermal oxide layer is within the range between about 50 Å and about 100 Å. 
     
     
       8. A method in accordance with claim 7 wherein said silicon rich oxide is deposited by chemical vapor deposition. 
     
     
       9. A method in accordance with claim 5 wherein said lower portion of said first polysilicon layer is deposited by LPCVD at a temperature of about 630° C. and said upper portion of said first layer of polysilicon is deposited as amorphous phase silicon by LPCVD at a temperature of about 560° C. 
     
     
       10. A method in accordance with claim 9 wherein the thickness of said silicon rich oxide layer is within the range between about 50 Å and about 200 Å and the thickness of said thermal oxide layer is within the range between about 50 Å and about 100 Å. 
     
     
       11. A method in accordance with claim 9 wherein said silicon rich oxide is deposited by chemical vapor deposition. 
     
     
       12. A method in accordance with claim 9 wherein a native polyoxide is provided as a boundary between said lower portion and said upper portion of said first polysilicon layer. 
     
     
       13. A method in accordance with claim 12 wherein the thickness of said silicon rich oxide layer is within the range between about 50 Å and about 200 Å and the thickness of said thermal oxide layer is within the range between about 50 Å and about 100 Å. 
     
     
       14. A method in accordance with claim 12 wherein said silicon rich oxide is deposited by chemical vapor deposition. 
     
     
       15. A method of forming a self-aligned flash MOS field effect transistor structure on a silicon semiconductor substrate with a source junction and a drain junction therein and said substrate having a surface a tunnel oxide structure deposited thereon, the improvement comprising, said tunnel oxide comprising a thermal oxide layer deposited upon said substrate and a silicon-rich-oxide layer deposited upon said thermal oxide layer, and   a flash memory gate structure deposited upon said silicon-rich-oxide layer.   
     
     
       16. A method in accordance with claim 1 wherein the thickness of said silicon rich oxide layer is within the range between about 50 Å and about 200 Å and the thickness of said thermal oxide layer is within the range between about 50 Å and about 100 Å. 
     
     
       17. A method in accordance with claim 16 wherein said silicon rich oxide is deposited by chemical vapor deposition. 
     
     
       18. A method in accordance with claim 15 wherein said silicon rich oxide is deposited by chemical vapor deposition.