Test flip-flop with an auxillary latch enabling two (2) bits of storage

Abstract

A scan flip-flop cell including a flip-flop, a feed-back path by which the output of the flip-flop can be controllably held, and a latch in the feedback path that allows the cell to store two bits of data simultaneously.

What is claimed is: 
     
       1. A scan flip-flop cell for receiving a serial scan input and a data input, and for providing a serial scan output and a data output, comprising: a flip-flop having an input and an output, wherein said flip-flop output provides the data output of the scan flip-flop cell;   delay means for providing a delayed replica of the output of said flip-flop, said delayed replica comprising the serial scan output of the scan flip-flop cell;   latching means responsive to said delayed replica of the flip-flop output for selectively latching said delayed replica pursuant to a latch control signal;   first selection means responsive to the serial scan input to the scan flip-flop cell, the output of said latching means, and said delayed replica of the flip-flop output for providing an output which is a replica of (a) the serial scan input, (b) said latch output, or (c) said replica of the flip-flop output as selected by first and second control signals;   second selection means responsive to the data input for the scan flip-flop cell and the output of said first selection means for providing an output which is a replica of (a) the first selection means output or (b) the data input to the scan flip-flop cell as selected by a third control signal, the output of said second selection means being provided to the input of said flip-flop such that the input to said flip-flop is selected by said first, second, and third control signals.   
     
     
       2. The scan flip-flop cell of claim 1 wherein said delay means comprises first and second serially connected inverters. 
     
     
       3. The scan flip-flop cell of claim 2 further including gating means responsive to the first and second control signals for providing the third control signal. 
     
     
       4. A scan flip-flop cell for receiving a serial scan input and a data input, and for providing a serial scan output and a data output, comprising: a flip-flop having an input and an output, wherein said flip-flop output provides the data output of the scan flip-flop cell;   delay means for providing a delayed replica of the output of said flip-flop, said delayed replica comprising the serial scan output of the scan flip-flop cell;   latching means responsive to said delayed replica of the flip-flop output for selectively latching said delayed replica pursuant to a latch control signal;   first multiplexing means responsive to the serial scan input to the scan flip-flop cell and to the output of said latching means for providing an output which is a replica of (a) the serial scan input or (b) said latch output as selected by a first multiplexing control signal;   second multiplexing means responsive to said delayed replica of the flip-flop output and to the output of said first multiplexing means for providing an output which is a replica of (a) said delayed replica of the flip-flop output or (b) the output of said first multiplexing means as selected by a second multiplexing control signal; and   third multiplexing means responsive to the data input for the scan flip-flop cell and the output of said second multiplexing means for providing an output which is a replica of (a) the data input for the scan flip-flop cell or (b) the output of said second multiplexing means as selected by a third multiplexing control signal, the output of said third multiplexing means being provided to the input of said flip-flop such that the input to said flip-flop is selected by the first, second, and third control signals.   
     
     
       5. The scan flip-flop cell of claim 4 wherein said delay means comprises first and second serially connected inverters. 
     
     
       6. The scan flip-flop cell of claim 5 further including gating means responsive to the first and second multiplexing control signal for providing the third multiplexing control signal.