Synchronous type semiconductor memory device operating in synchronization with an external clock signal

Abstract

In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

What is claimed is: 
     
       1. A semiconductor memory device, comprising: a plurality of memory cell array blocks each including (a) a plurality of memory cells arranged in rows and columns, (b) a plurality of pairs of bit lines arranged corresponding to the columns and each connecting memory cells on a corresponding column, and (c) a dummy bit line located at an end of an associated memory array block in parallel with said plurality of pairs of bit lines;   a plurality of local IO lines provided corresponding to said plurality of memory cell array blocks, each for supplying and receiving data to and from a selected memory cell in a corresponding memory cell array block;   a global IO line commonly provided to said plurality of local IO lines, for transferring data with a local IO line provided corresponding to a memory cell array block designated by a block designating signal; and   precharge means responsive to a precharge instructing signal for electrically connecting said dummy bit lines to corresponding local IO lines and for supplying a predetermined precharge potential onto said dummy bit lines.   
     
     
       2. A semiconductor memory device, comprising: a plurality of memory array blocks each including (a) a plurality of memory cells arranged in rows and columns, (b) a plurality of pairs of bit lines arranged corresponding to the columns and connecting memory cells on corresponding columns, and (c) a dummy bit line located at an end of an associated memory array block in parallel with the bit lines, and each said memory array block grouped into groups of columns;   a plurality of local IO lines provided corresponding to the groups of columns of respective memory array blocks, for transferring data to and from selected memory cells in corresponding groups of columns;   a plurality of global IO lines provided common to said plurality of memory array blocks and corresponding to said groups of columns of each of said plurality of memory array blocks;   connection means responsive to a block selection signal for connecting local IO lines provided for a selected memory array block to said plurality of global IO lines;   means responsive to a precharge signal for connecting each of said dummy bit line to a corresponding local IO line; and   means responsive to said precharge signal for precharging each of said dummy bit line to a predetermined potential.   
     
     
       3. A semiconductor memory device, comprising: a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns;   a plurality of sense amplifiers provided corresponding to said columns, each said sense amplifier responsive to a sense amplifier activation signal for sensing and amplifying a signal on a corresponding column;   a plurality of local IO lines provided for respective memory array blocks, each for transferring data to and from a selected memory cell in a corresponding memory array block;   a global IO line provided common to said plurality of local IO lines; and   connection means provided corresponding to each of said plurality of memory array blocks and responsive to the sense amplifier activation signal for connecting a corresponding local IO line and said global IO line.   
     
     
       4. A semiconductor memory device, comprising: a plurality of memory blocks arranged to form a matrix of rows and columns, each said memory block including a plurality of memory cells arranged in a matrix of rows and columns;   a plurality of local I/O lines provided corresponding to said plurality of memory blocks, for effecting data transfer to and from selected memory cells in corresponding memory blocks;   a plurality of global I/O lines provided common to memory blocks aligned in the column direction,   a plurality of sense drive signal lines provided corresponding to said plurality of memory blocks for transferring sense drive signals;   a plurality of sense amplifier means provided corresponding to said plurality of memory blocks and responsive to sense drive signals on corresponding sense drive signal lines for sensing and amplifying data signals of memory cells selected in corresponding memory blocks; and   connection means provided corresponding to said plurality of memory blocks and responsive to said sense drive signals for connecting local I/O lines for corresponding memory blocks to said plurality of global I/O lines.   
     
     
       5. The device according to claim 4, wherein each of said plurality of sense means includes a plurality of sense amplifiers provided corresponding to the columns of memory cells in a corresponding memory block, for sensing and amplifying data signals of memory cells selected in corresponding columns. 
     
     
       6. The device according to claim 4, wherein said plurality of local I/O lines includes local I/O lines shared between two memory blocks adjacent in the column direction. 
     
     
       7. The device according to claim 4, wherein said plurality of memory blocks are divided into two groups each including adjacent memory blocks in the column direction, and said plurality of global I/O lines includes a first global I/O lines includes a first global I/O line provided for memory blocks aligned in the column direction and included in one group of said two group and a second global I/O lines provided for the memory blocks aligned in the column direction and included in the other group of said two groups, and wherein said connection means includes means provided for particular memory blocks in said one group and adjacent to said the other group, for connecting corresponding local I/O lines to said first global I/O lines and means provided for memory blocks other than said particular memory blocks, for connecting corresponding local I/O lines to said second global I/O lines. 
     
     
       8. The device according to claim 4, wherein said plurality of global I/O lines includes global I/O lines disposed between memory blocks adjacent in the row direction. 
     
     
       9. A semiconductor memory device, comprising: a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns, and grouped into a first group of blocks and a second group of blocks;   a plurality of sense amplifiers provided, on both sides of respective memory array blocks, corresponding to said columns, one sense amplifier for each said column for sensing and amplifying a signal on a corresponding column;   a plurality of local IO lines arranged corresponding to said plurality of memory array blocks;   a first global line;   a second global IO line; and   connection means responsive to a block designating signal for connecting one block in each of said first and second group with said first and second global IO lines;   said connection means including (a) first connecting means provided for at least one memory array block in said first group and responsive to said block designating signal for connecting a corresponding local IO line to said first global IO line;   (b) second connecting means provided for the memory array blocks other than said at least one memory array blocks in said first group and responsive to said block designating signal for connecting a corresponding global IO line to said second global IO line;   (c) third connecting means provided for at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line to said second global IO line; and   (d) fourth connecting means provided for the memory array blocks other than said at least one memory array block in said second group and responsive to said block designating signal for connecting a corresponding local IO line with said first global IO line.     
     
     
       10. A semiconductor memory device, comprising: a plurality of memory arrays each including a plurality of memory cells arranged in rows and columns and each grouped into a plurality of blocks in a row direction, and including a word line shunt region provided between blocks adjacent in the row direction;   a plurality of local IO lines provided corresponding to said plurality of blocks and each for transferring a data signal to and from a selected memory cell in a corresponding block;   a plurality of global IO lines, one for a predetermined number of memory arrays, provided commonly to respective blocks in the predetermined number of memory arrays and in said word line shunt regions; and   connection means responsive to an array designation signal designating a memory array for connecting a corresponding local IO line in the designated memory array to a corresponding global IO line.   
     
     
       11. The device according to claim 10, further comprising a plurality of sense means provided for the respective blocks for sensing and amplifying data signals of memory cells selected in associated memory blocks in response to a sense drive signal, and wherein said connection means receives said sense drive signal as said array designation signal for operation. 
     
     
       12. A synchronous type semiconductor memory device operating in synchronization with an external clock signal and including a data output terminal, comprising: a plurality of data registers provided commonly to said data output terminal and receiving data in parallel from a plurality of simultaneously selected memory cells;   selection means responsive to a data read designation signal for sequentially selecting said data registers in a predetermined sequence;   latch means for latching data from a selected data register;   read means for transferring data latched in said latch means to said data output terminal; and   drive means responsive to said data read designation signal for driving said latch means and said read means.   
     
     
       13. The device according to claim 12, wherein said drive means drives said latch means and said read means in a pipelined manner. 
     
     
       14. The device according to claim 12, wherein said read means includes another latch means responsive to said drive means for latching data from said latch means. 
     
     
       15. The device according to claim 12, wherein said latch means includes a plurality of buffer means provided corresponding to said plurality of data registers and responsive to said selection means for transferring data of corresponding data registers, and a latch circuit for latching data from a selected buffer means. 
     
     
       16. The device according to clam 12, wherein each of said plurality of data registers includes, a preamplifier for amplifying a data signal from a selected memory cell,   a master latch for latching the data signal from said preamplifier,   transfer gate responsive to a transfer instruction signal generated after activation of said preamplifier, for transferring the latched data signal of said master latch, and   a slave latch for latching the data signal transferred from said transfer gate.   
     
     
       17. The device according to claim 12, wherein said selection means includes wrap address generation means responsive to said data read designation signal for generating a wrap address designating a data register in synchronization with said external clock signal. 
     
     
       18. The device according to claim 17, wherein said drive means includes latency storage means for storing a latency data defining the number of clock cycles required for appearance of a valid data at said data output terminal from application of a column selection instructing signal;   wrap length data storage means for storing a wrap length data defining the number of valid data successively read out from said data output terminal;   control means responsive to said column selection instructing signal and said data read designating signal for activating said wrap address generation means in synchronization with a clock signal of a clock cycle preceding by at least two clock cycles the clock cycle specified by the latency specified by the latency data and for deactivating said wrap address generation means after elapse of clock cycles of the number of wrap length specified by said wrap length data since activation of said wrap address generation means.   
     
     
       19. The device according to claim 16, further including data lines coupled to each said preamplifier for transferring data signal from the simultaneously selected memory cells to each said preamplifier, and means for driving said data lines to a predetermined potential in response to activation of each said preamplifier. 
     
     
       20. A synchronous semiconductor memory device operating in synchronization with an external clock signal having a predetermined pulse width, comprising: a plurality of banks each including a plurality of memory cells arranged in rows and columns;   a data output terminal provided in common to said plurality of banks;   cell selection means responsive to a bank designation signal designating a bank output of said plurality of banks and an address signal, for simultaneously selecting a plurality of memory cells in the designated bank;   a plurality of pipeline means provided corresponding to said plurality of banks and responsive to said bank designation signal and a data read designation signal instructing a data read operation for transferring data from the simultaneously selected memory cells sequentially in response to said external clock signal, and   read means provided in common to said plurality of pipeline means for transferring data from the designated pipeline means to said data output terminal in response to said data read designation signal and said external clock signal.   
     
     
       21. A synchronous type semiconductor memory device for taking an external signal and data in synchronization with a clock of a series of pulses, including a data output terminal and a plurality of data registers provided for said data output terminal for receiving and storing data read out from a plurality of simultaneously selected memory cells, said device comprising: wrap address generator means responsive to a data read designation signal and said clock for generating a wrap address for selecting a data register; and   read means responsive to said wrap address for transferring data in a data register selected by said wrap address to said data output terminal.   
     
     
       22. A synchronous type semiconductor memory device taking in a control signal, an address signal and data in synchronization with a clock of a predetermined pulse width, including a data output terminal and a plurality of data registers provided for said data output terminal for receiving in parallel and storing data of a plurality of simultaneously selected memory cells in a memory cell array having memory cells arranged in rows and columns, said device comprising: latency storage means for storing a latency data defining the number of clock cycles required for appearance of a valid data at said data output terminal from application of a column selection instructing signal;   wrap length data storage means for storing a wrap length data defining the number of valid data successively read out from said data output terminal;   wrap address generation means responsive to said clock and a data read designating signal for generating a wrap address for selecting said plurality of data registers in a predetermined sequence;   control means responsive to said column selection instructing signal and said data read designating signal for activating said wrap address generation means in synchronization with a clock of a clock cycle preceding by at least two clock cycles the clock cycle specified by the latency specified by the latency data and for deactivating said wrap address generation means after elapse of clock cycles of the number of wrap length specified by said wrap length data since activation of said wrap address generation means.   
     
     
       23. A synchronous type semiconductor memory device taking in a control signal, an address signal and data in synchronization with a clock signal of a series of pulses and in which a plurality of memory cells are simultaneously selected in a memory cell array having a multiplicity of memory cells arranged in rows and columns, comprising: first latch means responsive to a first control signal for latching in parallel data read out of said plurality of memory cells simultaneously selected;   second latch means responsive to a second control signal for latching data latched in said first latch means;   output means for sequentially supplying externally data latched in said second latch means in a predetermined sequence and in synchronization with said clock; and   control means responsive to a column selecting instruction applied in synchronization with said clock for generating said first and second control signal sequentially in this order.   
     
     
       24. A synchronous type semiconductor memory device taking in a control signal, an address signal and a data in synchronization with a clock of a series of pulses and including a memory cell array having a plurality of memory cells among which a predetermined number of memory cells are simultaneously selected, a valid data of a selected memory appearing at an output terminal upon elapse of a clock cycle or cycles specified by a latency after application of a column selection designating signal, said device comprising: first latch means for receiving in parallel and latching data read out from said predetermined number of memory cells simultaneously selected;   counting means activated in response to said column selection designating signal for counting a clock pulse;   second latch means for receiving and latching data latched in said first latch means;   output means for reading out data latched in said second latch means in a predetermined sequence for transference to said output terminal; and   transfer means responsive to a count of said counting means being less than the latency for transferring data latched in said first latch means to said second latch means.   
     
     
       25. The device according to claim 24, wherein said transfer means performs the transfer operation when said count is equal to the latency less two. 
     
     
       26. A synchronous type semiconductor memory device taking in an external signal and data in synchronization with a clock of a series of pulses and including a plurality of data registers for receiving in parallel and latching data read out from a plurality of memory cells simultaneously selected in a memory cell array having memory cells arranged in rows and columns and a data output terminal provided commonly to said plurality of data registers, comprising: latency storage means for storing a latency data indicating the number of clock cycles required for a valid data to appear at said data output terminal from when a column selection designating signal is applied;   wrap length data storage means for storing a wrap length data indicating the number of valid data successively read out from said data output terminal;   selection means responsive to said column selection designating signal for selecting a data register out of said plurality of data registers in a predetermined sequence;   output means for receiving data of a data register selected by said selection means to produce a read out data for transmission to said data output terminal; and   control means responsive to said column selection designating signal to be activated for counting a clock pulse and for bringing said output means into a data output enable state during a period in which a count is in a predetermined range.   
     
     
       27. The device according to claim 26, wherein said predetermined range covers the range between the latency minus one and a count not less than said wrap length. 
     
     
       28. The device according to claim 26, wherein said predetermined range is a range between a count equal to the latency minus one and a count equal to the wrap length plus one. 
     
     
       29. The device according to claim 26, wherein said control means includes divider means for frequency-dividing said clock by a predetermined dividing ratio and for shifting in phase the frequency-divided clock to generate a plurality of drive signals;   reference means responsive to said plurality of drive signals for generating and applying reference voltage to said output means as an operating power supply voltage thereof, and   adjust means for adjusting a driving capability of said reference means at least during a period in which said output means is enabled.   
     
     
       30. The device according to claim 29, wherein said reference means includes charge pump circuits provided corresponding to said plurality of drive signals in parallel with each other for generating said reference voltage through charge pumping operation responsive to corresponding drive signals. 
     
     
       31. The device according to claim 29, wherein said adjust means includes means responsive to a data read designating signal indicating data read mode of operation for transferring said clock to said divider means. 
     
     
       32. A synchronous type semiconductor memory device taking in an external signal and data in synchronization with a clock of a series of pulses, and including a plurality of banks each including (a) a memory array having a plurality of memory cells arranged in rows and columns and (b) a plurality of data registers for receiving in parallel and storing data read out from memory cells simultaneously selected in said memory array, and a data output terminal provided commonly to said plurality of banks, said device comprising: data transfer means provided corresponding to said plurality of data registers in each of said plurality of banks for transferring data received from corresponding data registers;   output means provided commonly to said plurality of banks for receiving data from a selected data register to produce a read out data for transmission to said data output terminal; and   control means activated in response to a column selection designating signal and a bank designating signal for counting a pulse of said clock to enable data transfer means provided for a bank designated by said bank designating signal during a period in which a count of said pulse is within a range of predetermined values.   
     
     
       33. The device according to claim 32, wherein said control means enables said data transfer means after said control means counts one clock pulse in response to application of said column selection designating signal. 
     
     
       34. The device according to claim 32, wherein said control means disables said data transfer means when said control means counts the clock pulses by a wrap length indicating a number of data successively read out after enabling said data transfer means. 
     
     
       35. A synchronous type semiconductor memory device taking in an external signal and input data in synchronization with a clock of a series of pulses and having a plurality of memory cells selected simultaneously in a memory array including a multiplicity of memory cells arranged in rows and columns, comprising: a data input terminal for receiving said input data;   a plurality of data registers provided receiving data from said data input terminal, for storing data to be written into the plurality of memory cells simultaneously selected;   register selection means responsive to a column selection instructing signal applied in synchronization with said clock for sequentially selecting said data registers in a predetermined order to couple a selected data register to said data input terminal; and   transfer means responsive to said column selection designating signal for transferring data in said data registers to corresponding memory cells on a unit of a predetermined number of data registers.   
     
     
       36. A synchronous type semiconductor memory device taking in external signals including a control signal, an address signal and an input data in synchronization with a clock of series of pulses and having a plurality of memory cells selected simultaneously in a memory array including memory cells arranged in rows and columns, comprising: a data input terminal for receiving said input data;   a plurality of first latch means sequentially coupled to said data input terminal in a predetermined order for storing data received at said data input terminal;   a plurality of second latch means provided corresponding to said plurality of first latch means for receiving and latching data latched in corresponding first latch means;   a plurality of data lines provided corresponding to the respective second latch means for transferring data to the corresponding memory cells in the simultaneously selected memory cells from corresponding second latch means; and   transfer control means responsive to a column selection instructing signal for generating a transfer control signal by which data is once latched in a first latch means and then the data is transferred to corresponding second latch means from said first latch means.   
     
     
       37. The device according to claim 36, wherein said transfer control means includes wrap data storage means for storing a wrap data indicating the number of data to be successively written in,   wrap address generator responsive to a data write designating signal designating a data write mode of operation for generating a wrap address for selecting and enabling said first latch means sequentially,   enable signal generator responsive to said wrap data and said clock for generating an enable signal for a period of clock cycles not less in number than the wrap data, and   transfer enable means responsive to said enable signal and said wrap address for enabling data transfer between the first and second latch means designated by the wrap address.   
     
     
       38. The device according to claim 36, wherein said transfer control means includes means enabling data transfer from second latch means and said data lines in units of a predetermined number of second latch means. 
     
     
       39. The device according to claim 36, wherein said transfer control means includes equalize means for driving said data lines to a predetermined potential level each data transfer of said predetermined number of second latch means to corresponding data line or lines.   
     
     
       40. The device according to claim 38, wherein said predetermined number is one. 
     
     
       41. The device according to claim 38, wherein said predetermined number is two. 
     
     
       42. The device according to claim 35, wherein said transfer control means includes means for bringing said data lines into an electrically floating state in a standby state. 
     
     
       43. The device according to claim 35, wherein said transfer control means includes means for maintaining said data lines to the predetermined potential in a standby state, and means responsive to said column selection designating signal for bringing said data lines into an electrically floating state. 
     
     
       44. A synchronous type semiconductor memory device taking in external signals including an external control signal, an address signal and an input data in synchronization with a clock of a series of pulses, comprising: divider means for frequency-dividing said clock and for shifting in phase a frequency-divided clock to generate a plurality of drive signals; and   generation means responsive to said plurality of drive signals for producing a reference voltage.   
     
     
       45. The device according to claim 44, further including output means coupled to a data output terminal and operating with said reference voltage as an operating power supply voltage, for effecting data output to said data output terminal. 
     
     
       46. The device according to claim 44, further including a memory cell array having memory cells arranged in rows and columns and a plurality of word lines arranged corresponding to said rows of memory cells, and wherein said reference voltage is supplied to a selected word line as a boosted word line drive signal. 
     
     
       47. The device according to claim 44, wherein said reference voltage is a negative voltage applied to a substrate layer, as a bias voltage, on which said synchronous type semiconductor memory device is formed. 
     
     
       48. The device according to claim 44, wherein said generation means includes a plurality of charge pump circuits provided i parallel and corresponding to said plurality of drive signals for producing said reference voltage through charge pumping operation responsive to the drive signals. 
     
     
       49. The device according to claim 45, further including control means for adjusting a charge supply capability of said generation means in response to a data read designation signal designating data output through said output means. 
     
     
       50. The device according to claim 49, wherein said control means includes means responsive to said data read designation signal for transferring said clock to said divider means. 
     
     
       51. The device according to claim 44, wherein said synchronous type semiconductor memory device includes a plurality of bank having the same configuration with each other and operable independently from each other, and said divider means includes a plurality of frequency-dividers provided corresponding to said plurality of banks, each for frequency-dividing said clock to generate the plurality of drive signals, and a plurality of generators provided corresponding to said plurality of frequency-dividers for generating the reference voltage, and wherein said synchronous semiconductor memory device further includes means responsive to a bank designation signal designating a bank in said plurality of banks for enabling only a frequency-provided corresponding to the designated bank. 
     
     
       52. The device according to claim 44, further including a plurality of data output terminals and a plurality of output circuits provided corresponding to said plurality of data output terminals and receiving said reference voltage as an operating power supply voltage, setting means for setting data determining the number of data output terminals available among said plurality of data output means, and adjust means responsive to said setting means for adjusting a charge supply capability of said generation means. 
     
     
       53. The device according to claim 52, wherein said adjust means includes means responsive to said setting means for selectively transferring a predetermined number of clock signal or signals to said generation means. 
     
     
       54. A synchronous type semiconductor memory device taking in external signals including a control signal, an address signal and an input data in synchronization with a clock of a series of pulses, comprising: setting means for setting data determining the number of data input and output terminals for receiving input and output data;   means for frequency-dividing said clock by a predetermined dividing ratio and for shifting in phase the frequency-divided clock to generate a plurality of drive signals;   reference means responsive to said plurality of drive signals for generating a reference voltage; and   means for adjusting a driving capability of said reference means in accordance with the data set by setting means.   
     
     
       55. A synchronous type semiconductor memory device taking in a control signal, an address signal and an input data in synchronization with a clock of a series of pulses, comprising: a plurality of banks having the same configuration with each other and operable independently from each other and each including a memory array of a plurality of memory cells; and   a plurality of reference means provided corresponding to said plurality of banks and responsive to said clock for generating reference voltages for corresponding banks.   
     
     
       56. A synchronous semiconductor memory device operating in synchronization with a clock signal having a predetermined pulse width, comprising: a memory array having a plurality of memory cells,   a data input terminal receiving a write data,   a plurality of data latch means sequentially coupled to receive data from said data input terminal,   a data bus provided for said plurality of data latch means for transferring data between said plurality of data latch means and memory cells simultaneously selected in said memory array,   drive means responsive to a data write designation signal and said clock signal for driving said data bus to a predetermined potential each predetermined number of clock signal or signals since application of said data write designation signal.   
     
     
       57. The device according to claim 56, wherein said drive means includes storage means for storing a wrap data indicating the number of data to be written successively, and counter means responsive to said data write designation signal for counting said clock signal, and means for driving said data bus to said predetermined potential when said counter means counts said clock signal a number of times equal in number to said wrap data after application of said data write designating signal. 
     
     
       58. The device according to claim 56, wherein said drive means includes means responsive to said data write designation signal for bringing the data bus into an electrically floating state, and means for driving the data bus at the predetermined potential. 
     
     
       59. The device according to claim 56, wherein said drive means includes means for bringing said plurality of data bus into an electrically floating state in a standby state. 
     
     
       60. The device according to claim 56, wherein said predetermined number is one. 
     
     
       61. The device according to claim 56, wherein said predetermined number is two. 
     
     
       62. The device according to claim 56, wherein said data bus includes a plurality of data lines provided corresponding to the respective data latch means and each said data line includes a pair of signal lines transferring data signals complementary to each other, and said drive means includes means for electrically connecting the signal lines in each said pair of signal lines. 
     
     
       63. The device according to claim 56, wherein said plurality of data latch means comprises a plurality of data registers provided in parallel with each other and sequentially coupled to said data input terminal. 
     
     
       64. The device according to claim 56, further including, a data output terminal,   a read data bus for transferring data from the selected memory cells,   read latch means for receiving data from said read data bus for output to said data output terminal,   transfer means for transferring data from said read data bus to said read latch means, and   bus drive means for driving said read data bus to the predetermined potential when said transfer data from said read data bus to said read latch means.   
     
     
       65. The device according to claim 64, wherein said read latch means comprises a plurality of read data registers sequentially coupled to said data read terminal, and said read data bus comprises a plurality of data lines provided corresponding to said plurality of read data registers for transfer in parallel data to said plurality of read data registers. 
     
     
       66. The device according to claim 64, wherein said bus drive means includes means responsive to a data read designation signal for bringing said read data bus into an electrically floating state, and means for driving said read data bus to the predetermined potential in a standby state. 
     
     
       67. The device according to claim 64, wherein said drive means includes means for maintaining said read data bus in an electrically floating state in a standby state. 
     
     
       68. A synchronous type semiconductor memory device operating in synchronization with a clock signal having a predetermined pulse width, comprising: a data input terminal receiving a write data;   a mask data input terminal for receiving a mask data indicating whether the write data at said data input terminal should be masked;   internal mask means responsive to said clock signal for generating an internal mask signal;   control means responsive to said clock signal and said mask data for resetting said internal mask signal when said mask data permits writing of the write data.   
     
     
       69. The device according to claim 68, wherein said internal mask means comprises flip-flop means set in response to a leading edge of said clock signal, and said control means includes latch means responsive to said leading edge of said clock signal for latching the mask data received at said mask data input terminal, and delay means for delaying an output of said latch means for application to said latch means for resetting said flip-flop when said mask data permits the writing of the write data. 
     
     
       70. The device according to claim 69, wherein said latch means comprises a dynamic latch responsive to the leading edge of said clock signal for latching said mask data and responsive to a trailing edge of said clock signal for being reset to bring complementary outputs thereof at a predetermined potential. 
     
     
       71. The device according to claim 70, wherein said latch means is adapted to be operable only when an access is made to said synchronous type semiconductor memory device is made.