Method for fabricating a triple self-aligned bipolar junction transistor
Abstract
A self-aligned process for fabricating high performance bipolar transistors for integrated circuits includes the formation of a collector contact and intrinsic collector region within an opening at the face of a semiconductor substrate. In particular, layers of oxide and polysilicon are formed on the surface of a substrate. An opening is then formed in both layers followed by the implantation of a buried collector region into the substrate at the exposed substrate face through the opening. Polysilicon contacts to the buried layer are then formed on the sidewalls of the opening. These contacts join with the polysilicon layer to form a collector contact. An oxide is then grown on the collector contact. A monocrystalline intrinsic collector is then formed from the exposed substrate face adjacent said collector contact. In this manner, the buried collector, collector contact and intrinsic collector are all formed in a self-aligned manner. Emitter and base regions may then be formed in the intrinsic collector, using techniques to form a completely self-aligned device.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A method of manufacturing a bipolar transistor comprising the steps of: providing a semiconductor substrate having a buried collector region therein at a face thereof and a first insulating layer on the face, said first insulating layer having an opening therethrough which defines a sidewall and exposes said buried collector region; forming a conductive collector contact layer on the sidewall which electrically contacts said buried collector region in the opening and extends onto a top surface of said first insulating layer; growing a monocrystalline region on the face, from said exposed buried collector region; and forming base and emitter regions in said monocrystalline region; and wherein said conductive collector contact layer forming step comprises the steps of: forming a first polycrystalline silicon layer on the top surface of said first insulating layer; forming a second polycrystalline silicon layer on said exposed buried collector region, on said sidewall and on said first polycrystalline silicon layer; and anisotropically etching said second polycrystalline silicon layer from said exposed buried collector region.
2. A method of manufacturing a bipolar transistor comprising the steps of: providing a semiconductor substrate having a buried collector region therein at a face thereof and a first insulating layer on the face, said first insulating layer having an opening therethrough which defines a sidewall and exposes said buried collector region; forming a conductive collector contact layer on the sidewall which electrically contacts said buried collector region in the opening and extends onto a top surface of said first insulating layer; forming a second insulating layer on said conductive collector contact layer; growing a monocrystalline region on the face, from said exposed buried collector region; and forming base and emitter regions in said monocrystalline region; and wherein said step of growing a monocrystalline region comprises the step of growing said monocrystalline region from the exposed buried collector region and onto a top surface of said second insulating layer.
3. A method of manufacturing a bipolar transistor comprising the steps of: providing a semiconductor substrate having a first insulating layer thereon and an opening therethrough which defines a sidewall of said first insulating layer and exposes a portion of a face of said substrate; forming a buried collector region in the exposed portion of said substrate; forming a conductive collector contact layer on the sidewall which electrically contacts said buried collector region in the opening and extends onto a top surface of said first insulating layer; forming a second insulating layer on said conductive collector contact layer; growing a first monocrystalline region from the exposed portion of said face onto said second insulating layer; and laterally growing a second monocrystalline region from said first monocrystalline region onto a top surface of said second insulating layer.
4. The method of claim 3 further comprising the steps of: forming a monocrystalline intrinsic base region in said first monocrystalline region; and forming an monocrystalline extrinsic base region in said laterally grown second monocrystalline region.
5. The method of claim 4 further comprising the step of: forming an emitter region in said intrinsic base region.
6. The method of claim 5 further comprising the step of: forming an emitter contact on said emitter region; and forming a base contact on said monocrystalline extrinsic base region.
7. A method of manufacturing a bipolar transistor comprising the steps of: forming a first insulating layer on the face of a silicon semiconductor substrate; forming a first polycrystalline silicon layer on said first insulating layer; forming an opening through said first insulating layer and said first polycrystalline silicon layer, for exposing said face of said semiconductor substrate and for defining a sidewall in said first insulating layer and said first polycrystalline silicon layer; forming a buried collector region in said semiconductor substrate at the exposed face through said opening; forming a second polycrystalline silicon layer on said first polycrystalline silicon layer, on said sidewall and on said exposed face; anisotropically etching said second polycrystalline silicon layer to remove said second polycrystalline layer on the exposed face; forming a second insulating layer on said first and said second polycrystalline layers; growing a monocrystalline silicon region from said exposed face to fill said opening and to extend laterally onto the top surface of said second insulating layer; and forming base and emitter regions in said monocrystalline silicon region.
8. The method of claim 7 further comprising the steps of: forming a base region in said grown monocrystalline region in said opening; and forming a base contact region in said laterally grown monocrystalline region on said second insulating layer.
9. The method of claim 8 further comprising the step of: forming an emitter region in said base region.
10. The method of claim 9 further comprising the step of: forming a base contact on said base region.
11. A method of fabricating a bipolar transistor comprising the steps of: providing a semiconductor substrate having a buried collector region therein at one face thereof, a first insulating layer having an opening therethrough for exposing said buried collector region and defining a sidewall in said first insulating layer, a conductive collector contact on said sidewall electrically contacting said buried collector region and extending onto the top surface of said first insulating layer, a second insulating layer on said conductive collector contact and a monocrystalline region in said opening extending from said exposed face and onto said second insulating layer; and forming base and emitter regions in said monocrystalline region.
12. A method of manufacturing a bipolar transistor comprising the steps of: providing a semiconductor substrate having a face thereon; forming a first insulating layer having an opening therein which exposes a portion of the face and defines a first sidewall of the first insulating layer, on the substrate; forming a buried collector region in the substrate, at the exposed portion of the face; forming a conductive collector contact layer which electrically contacts the buried collector region, on the first sidewall; forming a second insulating layer on the conductive collector contact layer; forming a monocrystalline region on the buried collector region and adjacent the second insulating layer; forming a monocrystalline intrinsic base region in the monocrystalline region; forming a monocrystalline extrinsic base region from the monocrystalline region, on the second insulating layer; and forming a base contact on the monocrystalline extrinsic base region.
13. The method of claim 12, wherein said monocrystalline extrinsic base region forming step comprises the step of laterally growing the monocrystalline extrinsic base region on the second insulating layer using lateral selective epitaxial growth.
14. The method of claim 12 wherein said monocrystalline extrinsic base region forming step comprises the steps of: forming an insulating cap on a top surface of the monocrystalline region; defining a seed hole which exposes the monocrystalline region, between the insulating cap and the second insulating layer; and forming the monocrystalline extrinsic base region from the seed hole.
15. The method of claim 14, wherein said second insulating layer forming step includes forming the second insulating layer on a sidewall and on a top surface of the conductive collector contact layer.
16. A method of manufacturing a bipolar transistor having monocrystalline intrinsic and extrinsic base regions, comprising the steps of: forming a first insulating layer on a semiconductor substrate; forming a buried collector region in the semiconductor substrate, adjacent the first insulating layer; forming a conductive collector contact layer which electrically contacts the buried collector region and extends onto the first insulating layer; forming a monocrystalline region on the buried collector region; forming a monocrystalline intrinsic base region in the monocrystalline region; forming a monocrystalline extrinsic base region from the monocrystalline region using selective epitaxial growth; forming a collector contact on the conductive collector contact layer; and forming a base contact on the monocrystalline extrinsic base region.
17. The method of claim 16, wherein said monocrystalline region forming step is preceded by the step of forming a second insulating layer on the conductive collector contact layer.
18. The method of claim 17, wherein said monocrystalline extrinsic base region forming step comprises the step of growing a monocrystalline extrinsic base region from the monocrystalline region and on the second insulating layer, using lateral selective epitaxial growth.Cited by (0)
No later patents cite this yet.
References (0)
No backward citations on record.