Formation of 3-dimensional silicon silicide structures

Abstract

An epitaxial conductor and a method for forming buried conductor patterns is described incorporating a layer of single crystalline silicon, a pattern formed therein such as a trench, a layer of metal silicide epitaxial formed on the bottom surface of the pattern or trench, a layer of silicon epitaxially formed thereover, and a layer of metal silicide epitaxially formed over the silicon layer. The invention overcomes the problem of twinning defects in the top surface of epitaxial silicide layers.

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is: 
     
       1. An epitaxial conductor comprising: a substrate of single crystalline semiconductor material selected from the group consisting of silicon and alloys thereof,   a first trench formed in said substrate having sidewall surfaces and a bottom surface,   a first layer of single crystalline metal silicide epitaxially formed on said bottom surface,   a second layer of single crystalline semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said first layer, and   a third layer of single crystalline metal silicide epitaxially formed on said second layer,   said first and second layers being in twinning relationship to said substrate,   said third layer being in twinning relationship to said first and second layers, and   said third layer having the same crystallographic orientation as said substrate.   
     
     
       2. The epitaxial conductor of claim 1 wherein said metal silicide is selected from the group consisting of cobalt silicide and nickel silicide. 
     
     
       3. The epitaxial conductor of claim 1 further including a fourth layer of single crystalline semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said third layer. 
     
     
       4. The epitaxial conductor of claim 3 wherein said fourth layer of semiconductor material has a thickness to substantially fill said trench. 
     
     
       5. The epitaxial conductor of claim 3 wherein said fourth layer of semiconductor material has the same crystallographic orientation as said substrate of crystalline semiconductor material. 
     
     
       6. The epitaxial conductor of claim 1 wherein said first layer of metal silicide has a thickness in the range front 10 to 22 Å. 
     
     
       7. The epitaxial conductor of claim 1 wherein said second layer of semiconductor material has a thickness in the range from 10 to 22 Å. 
     
     
       8. The epitaxial conductor of claim 1 wherein said substrate has a (111) silicon surface. 
     
     
       9. The epitaxial conductor of claim 1 wherein said substrate has a silicon surface selected from the group consisting of (100) and (001). 
     
     
       10. The epitaxial conductor or claim 6 wherein said third layer of metal silicide has a thickness in the range from 1000 to 2000 Å. 
     
     
       11. The epitaxial conductor of claim 1 wherein said first layer of metal silicide has a thickness in the range from 1000 to 2000 Å. 
     
     
       12. The epitaxial conductor of claim 11 wherein said third layer of metal silicide has a thickness in the range from 10 to 22 Å. 
     
     
       13. The epitaxial conductor of claim 1 wherein said substrate further includes a plurality of trenches having said first, second, and third layers to form a pattern of conductors in said plurality of trenches in said substrate. 
     
     
       14. The epitaxial conductor of claim 3 wherein the upper surface of said fourth layer of semiconductor material is coplanar with said upper surface of said substrate. 
     
     
       15. The epitaxial conductor of claim 3 further including a fifth layer of semiconductor material selected from the group consisting of silicon and alloys thereof formed on the upper surface of said substrate and fourth layers. 
     
     
       16. The epitaxial conductor of claim 15 wherein the upper surface of said fourth layer of semiconductor material is coplanar with said upper surface of said substrate. 
     
     
       17. The epitaxial conductor of claim 15 further including: a second trench formed in said fifth layer having sidewall surfaces and a bottom surface,   a sixth layer of metal silicide epitaxially formed on said bottom surface,   a seventh layer of semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said sixth layer, and   an eighth layer of metal silicide epitaxially formed on said seventh layer.   
     
     
       18. The epitaxial conductor of claim 17 further including a first pattern of first trenches in said substrate having said first, second, and third layers therein and a second pattern of second trenches in said fifth layer having said sixth, seventh, and eighth layers therein.   
     
     
       19. The epitaxial conductor of claim 1 wherein said first trench is formed in said first layer and said substrate. 
     
     
       20. An epitaxial conductor comprising: a substrate,   a first layer of single crystalline semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said substrate, said first layer having a (111) silicon surface,   a first trench formed in said first layer having sidewall surfaces and a bottom surface,   a second layer of metal silicide epitaxially formed on said bottom surface,   a third layer of semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said second layer, and   a fourth layer of metal silicide epitaxially formed on said third layer.   
     
     
       21. An epitaxial conductor comprising: a substrate,   a first layer of single crystalline semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said substrate, said first layer has a silicon surface selected from the group consisting of (100) and (001),   a first trench formed in said first layer having sidewall surfaces and a bottom surface,   a second layer of metal silicide epitaxially formed on said bottom surface,   a third layer of semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said second layer, and   a fourth layer of metal silicide epitaxially formed on said third layer.   
     
     
       22. An epitaxial conductor comprising: a substrate,   a first layer of single crystalline semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said substrate,   a first trench formed in said first layer having sidewall surfaces and a bottom surface,   a second layer of metal silicide epitaxially formed on said bottom surface, said second layer of metal silicide having a thickness in the range from 10 to 22 Å,   a third layer of semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said second layer, and   a fourth layer of metal silicide epitaxially formed on said third layer, said fourth layer of metal silicide having a thickness in the range from 1000 to 2000 Å.   
     
     
       23. An epitaxial conductor comprising: a substrate,   a first layer of single crystalline semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said substrate,   a first trench formed in said first layer having sidewall surfaces and a bottom surface,   a second layer of metal silicide epitaxially formed on said bottom surface, said second layer of metal silicide having a thickness in the range from 1000 to 2000 Å,   a third layer of semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said second layer, and   a fourth layer of metal silicide epitaxially formed on said third layer, said fourth layer of metal silicide having a thickness in the range from 10 to 22 Å.   
     
     
       24. An epitaxial conductor comprising: a substrate,   a first layer of single crystalline semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said substrate,   a first trench formed in said first layer having sidewall surfaces and a bottom surface,   a second layer of metal silicide epitaxially formed on said bottom surface,   a third layer of semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said second layer,   a fourth layer of metal silicide epitaxially formed on said third layer,   a fifth layer of semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said fourth layer, and   a sixth layer of semiconductor material selected from the group consisting of silicon and alloys thereof formed on the upper surface of said first and fifth layers.   
     
     
       25. The epitaxial conductor of claim 24 wherein the upper surface of said fifth layer of semiconductor material is coplanar with said upper surface of said first layer. 
     
     
       26. The epitaxial conductor of claim 24 further including: a second trench formed in said sixth layer having sidewall surfaces and a bottom surface,   a seventh layer of metal silicide epitaxially formed on said bottom surface,   an eight layer of semiconductor material selected from the group consisting of silicon and alloys thereof epitaxially formed on said seventh layer, and   a ninth layer of metal silicide epitaxially formed on said eighth layer.   
     
     
       27. The epitaxial conductor of claim 26 further including a first pattern of first trenches in said first layer having said second, third and fourth layers therein and a second pattern of second trenches in said sixth layer having said seventh, eight, and ninth layers therein.