Method of making thin film transistor and a silicide local interconnect

Abstract

A method of fabricating a transistor on a wafer including: forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.

What is claimed is: 
     
       1. A method of fabricating a transistor on a wafer comprising: a. forming a doped polysilicon transistor body with source/drain regions on top of an insulator;   b. forming a gate oxide on top of said transistor body;   c. depositing a first metal layer over said transistor body, and a portion of said insulator;   d. annealing said first metal layer to create silicided regions above said source/drain regions, then removing unsilicided portions of said first metal layer, and then depositing a second metal layer over said transistor body;   e. forming an amorphous silicon layer over said second metal layer, said amorphous silicon layer patterned in a gate and a local interconnect configuration;   f. annealing to form silicided to form silicided regions above said source/drain regions within said transistor body, and where said second metal layer reacts with said amorphous silicon layer to create a silicided gate and a silicided local interconnect; and   g. etching unsilicided metal to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.   
     
     
       2. The method of claim 1, wherein said source/drain regions within said transistor body are doped before said formation of said silicided gate. 
     
     
       3. The method of claim 1, wherein said source/drain regions within said transistor body are doped after formation of said gate, whereby said doping is self-aligned with said gate. 
     
     
       4. The method of claim 1, wherein sidewall spacers are formed along said transistor body. 
     
     
       5. The method of claim 1, wherein said metal is titanium and said silicide is titanium silicide. 
     
     
       6. The method of claim 1, wherein said metal is cobalt and said silicide is cobalt silicide. 
     
     
       7. The method of claim 1, wherein said metal is a refractory metal and the silicide is the corresponding silicide compound. 
     
     
       8. The method of claim 1, wherein said insulator is on top of a single crystal silicon layer and said silicon layer serves as a substrate. 
     
     
       9. The method of claim 1, wherein said insulator is on top of a polycrystalline silicon layer. 
     
     
       10. The method of claim 1, wherein said insulator is formed on top of a single crystal silicon on insulator substrate. 
     
     
       11. The method of claim 1, wherein said gate is formed simultaneously with a local interconnect.