Nonvolatile semiconductor memory apparatus

Abstract

A nonvolatile semiconductor memory apparatus of the present invention has a feature that charging of a control gate of a nonselective memory cell is simultaneously executed upon charging of a bit line. That is, in the case of normal reading (random accessing), charging of the control gate of the nonselective memory cell is conducted previously to at least one of source and drain side selective gates. Then, when the threshold value of the memory cell in the case of erasing the cell is judged, in a read mode, charging of the selective gate is started by delaying from the timing of charging the control gate of the nonselective memory cell to negative. That is, the selective gate is closed until the control gate is completely set to a negative testing voltage to prevent the bit line from being discharged. After the control gate is completely set to the negative testing voltage, the selective gate is delayed to be charged so that the selective gate is turned ON.

What is claimed is: 
     
       1. A nonvolatile semiconductor memory device comprising: a memory cell array formed of a plurality of memory cells which are electrically rewritable, each of said memory cells including a MOS transistor having a control gate;   a plurality of selective gate transistors, each having a selective gate and coupled to at least one of said plurality of said memory cells;   a bit line coupled to at least one of said plurality of selective transistors;   a source line coupled to said bit line via at least one of said selective gate transistors and at least one of said memory cells; and   charging means for charging the selective gate of one of the selective gate transistors and the control gate of one of said memory cells at different timings in a read operation.   
     
     
       2. The nonvolatile semiconductor memory device according to claim 1, wherein: said charging means includes means for charging the control gate of said one of said memory cells prior to charging the selective gate of said one of the selective gate transistors.   
     
     
       3. The nonvolatile semiconductor memory device according to claim 1, wherein: a preselected number of said plurality of memory cells form a memory cell unit, and said bit line and said source line are coupled to said memory cell unit.   
     
     
       4. The nonvolatile semiconductor memory device according to claim 1, wherein: a preselected number of said plurality of memory cells are connected in series to form a NAND-type memory cell.   
     
     
       5. The nonvolatile semiconductor memory device according to claim 1, wherein: said charging means includes means for charging the control gate of said one of said memory cells and said bit line at the same time.   
     
     
       6. The nonvolatile memory device according to claim 1, wherein said charging means charges the selective gate of one of the selective gate transistors and the control gate of one of said memory cells at different timing during a data reading operation. 
     
     
       7. A nonvolatile semiconductor memory apparatus, comprising: a plurality of memory cells being electrically rewritable, each having a MOS transistor including a drain, a source and a control gate, so connected in series that said drain of one transistor and said source of another transistor adjacent thereto are formed in a shared region to form a memory cell array having a drain end and a source end, said memory cell array being divided into a plurality of blocks;   a first selective gate transistor having a first end and a second end connected to said drain end;   a bit line connected to said first end of said first selective gate transistor;   a second selective gate transistor connected to said source end; and   charging means for charging said control gate of at least one nonselective memory cell included in one of said blocks earlier than at least one of said first and second selective gate transistors.   
     
     
       8. The nonvolatile semiconductor memory apparatus according to claim 7, wherein said charging means simultaneously charges the control gate of said at least one nonselective memory cell and said bit line. 
     
     
       9. The nonvolatile semiconductor memory apparatus according to claim 7, further comprising: means for discharging said control gate of said at least one nonselective memory cell after the discharging of at least one of said first and second selective gate transistors.   
     
     
       10. A nonvolatile semiconductor memory device according to claim 7, wherein a preselected number of said plurality of memory cells are connected in series to form a NAND-type memory cell unit, and   said bit line and said source line are coupled to said NAND-type memory cell unit.   
     
     
       11. The nonvolatile semiconductor memory device according to claim 10, wherein said charging means includes means for charging said control gates of said NAND-type memory cell unit before charging of said selective gate of said selective gate transistor. 
     
     
       12. The nonvolatile semiconductor memory device according to claim 11, wherein said memory cell further comprising a tunnel insulating layer and charge storage layer in which charges, to define data of said memory cell, are extracted or stored through said tunnel insulating layer. 
     
     
       13. An electrically erasable nonvolatile memory device according to claim 11, wherein said charging means is activated during data read operation. 
     
     
       14. A nonvolatile semiconductor memory device according to claim 7, wherein a preselected number of said plurality of memory cells form a memory cell unit,   said bit line and said source line are coupled to said memory cell unit, and   said charging means includes means for charging said control gate and said bit line at the same time.   
     
     
       15. The nonvolatile semiconductor memory device according to claim 7, wherein said charging means includes means for charging control gates of said memory cell unit before charging of said selective gate of said selective gate transistor. 
     
     
       16. An electrically erasable nonvolatile memory device according to claim 15, wherein said memory cell further comprising a tunnel insulating layer and charge storage layer in which charges, to define data of said memory cell, are extracted or stored through said tunnel insulating layer. 
     
     
       17. An electrically erasable nonvolatile memory device according to claim 15, wherein said charging means is activated during data read operation. 
     
     
       18. An electrically erasable nonvolatile memory device comprising: a memory cell array including a plurality of memory cells, each comprising a MOS transistor having a control gate, said plurality of said memory cells constituting a memory cell unit which has two end portions;   a selective gate transistor having a selective gate and being coupled to one end portion of said memory cell unit;   a bit line coupled to said memory cell unit via said selective gate transistor;   a source line coupled to the other end portion of said memory cell unit; and   charging means for charging control gates of the MOS transistor prior to charging said selective gate of said selective gate transistor.   
     
     
       19. The electrically erasable nonvolatile memory device according to claim 18, wherein: each of said memory cells further comprises a tunnel insulating layer and charge storage layer in which charges, to define data of said memory cell, are extracted or stored through said tunnel insulating layer.   
     
     
       20. The electrically erasable nonvolatile memory device according to claim 18, wherein: said charging means is activated during a data read operation.   
     
     
       21. The electrically erasable nonvolatile memory device according to claim 18, wherein: said memory cells are connected in series to provide a NAND structure.   
     
     
       22. The electrically erasable nonvolatile memory device according to claim 18, wherein: said charging means includes means for charging said control gates of said memory cells and said bit line at the same time.