Semiconductor integrated device and wiring correction arrangement therefor

Abstract

An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus. With this arrangement, the leakage current path formed by a defective element or circuit left unused in conventional circuits is cut, and the product yield of the device is raised significantly. This arrangement can be used for a variety of memory or logic devices, including DRAMs, SRAMs, multiport memories and gate arrays.

We claim: 
     
       1. A method of saving a defective semiconductor memory having a plurality of bit lines, a redundant bit line and a plurality of MOSFETs coupled to said plurality of bit lines and said redundant bit line, respectively, comprising the steps of: (a) forming a voltage supply line, on a semiconductor substrate, which is capable of providing said plurality of bit lines and a redundant bit line with a voltage through said plurality of MOSFETs, respectively;   (b) testing said defective semiconductor memory to locate a defective bit line in said plurality of bit lines;   (c) selecting said redundant bit line instead of said defective bit line; and   (d) cutting said voltage supply line at a predetermined place so that said voltage supply line is incapable of providing said defective bit line with said voltage through the corresponding MOSFET.   
     
     
       2. A method according to claim 1, further comprising: (e) setting address information of said defective bit line into a memory circuit formed in said defective semiconductor memory.   
     
     
       3. A method according to claim 2, wherein said step (e) includes: (e1) cutting a fuse element in said memory circuit, wherein cutting said fuse element is performed in the same process as cutting said voltage supply line.   
     
     
       4. A method of saving a defective semiconductor memory having a plurality of bit lines, a redundant bit line and a plurality of precharge circuits coupled to said plurality of bit lines and said redundant bit line, respectively, comprising the steps of: (a) forming a precharge voltage supply line, on a semiconductor substrate, which is capable of providing said plurality of bit lines and a redundant bit line with a precharge voltage through said plurality of precharge circuits, respectively;   (b) testing said defective semiconductor memory to locate a defective bit line in said plurality of bit lines;   (c) selecting said redundant bit line instead of said defective bit line; and   (d) cutting said precharge voltage supply line at a predetermined place so that said precharge voltage supply line is incapable of providing said defective bit line with said precharge voltage.   
     
     
       5. A method according to claim 4, further comprising: (e) setting address information of said defective bit line into a memory circuit formed in said defective semiconductor memory.   
     
     
       6. A method according to claim 5, wherein said step (e) includes: (e1) cutting a fuse element in said memory circuit, wherein cutting of said fuse element is performed in the same process as cutting said precharge voltage supply line.   
     
     
       7. A method of saving a defective semiconductor memory having a plurality of bit lines, a redundant bit line and a plurality of sense amplifiers coupled to said plurality of bit lines and said redundant bit line, respectively, comprising the steps of: (a) forming a power supply line, on a semiconductor substrate, which is capable of providing said plurality of sense amplifiers with an operation voltage;   (b) testing said defective semiconductor memory to locate a defective bit line in said plurality of bit lines;   (c) cutting said power supply line at a predetermined place so that said power supply line is incapable of providing the sense amplifier corresponding to said defective bit line with said operation voltage.   
     
     
       8. A method according to claim 7, further comprising: (e) setting address information of said defective bit line into a memory circuit formed in said defective semiconductor memory.   
     
     
       9. A method according to claim 8, wherein said step (e) includes: (e1) cutting a fuse element in said memory circuit, wherein cutting of said fuse element is performed in the same process as cutting said power supply line.   
     
     
       10. A semiconductor memory comprising: a plurality of bit lines;   a redundant bit line to be selected instead of a predetermined one of said bit lines if it is determined that said predetermined one of said bit lines is defective;   a plurality of first precharge circuits coupled to said plurality of bit lines, respectively;   a second precharge circuit coupled to said redundant bit line;   a common control line coupled to said plurality of first precharge circuits, and said second precharge circuit; and   a precharge voltage supply line coupled to said plurality of first precharge circuits and said second precharge circuit;   wherein a predetermined one of said first precharge circuits coupled to said defective bit line is placed in a state of being non-coupled to said precharge voltage supply line by cutting said precharge voltage supply line at a predetermined place so that said predetermined one of said first precharge circuits is substantially inoperative thereby preventing voltage from being provided to said defective bit line.   
     
     
       11. A semiconductor memory according to claim 10, wherein said plurality of first precharge circuits and said third precharge circuit are driven by control signals of said common control line. 
     
     
       12. A semiconductor memory comprising: a plurality of bit lines;   a redundant bit line to be selected instead of a predetermined one of said bit lines if it is determined that said predetermined one of said bit lines is defective;   a plurality of first sense amplifiers coupled to said plurality of bit lines, respectively;   a second sense amplifier coupled to said redundant bit line; and   a power supply line coupled to said plurality of first sense amplifiers and said second sense amplifier;   wherein a predetermined one of said first sense amplifiers coupled to said defective bit line is in a state of being non-coupled to said power supply line by cutting said power supply line at a predetermined place so that said predetermined one of said first sense amplifiers is inoperative, thereby preventing voltage from being provided to said defective bit line.   
     
     
       13. A semiconductor memory according to claim 12, wherein said cutting power supply line prevents leakage current from flowing from said power supply line toward a ground line through said defective bit line.