Inventor

ISHIHARA MASAMICHI

JP72 patents

⚠️ This page may combine multiple inventors who share the name “ISHIHARA MASAMICHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ISHIHARA MASAMICHI

HITACHI LTD

Multi-chip semiconductor package

Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement

Semiconductor device

Semiconductor device with lead structure within the planar area of the device

Semiconductor memory device with low-house pads for electron beam test

Resin-encapsulated semiconductor device

Semiconductor memory device

Semiconductor integrated circuit device, and process and apparatus for manufacturing the same

Sealed stacked arrangement of semiconductor devices

Semiconductor memory device

Semiconductor memory

Semiconductor memory having multiple continuous access functions

Dynamic type semiconductor memory device

Semiconductor memory having both a refresh operation cycle and a normal operation cycle and employing an address non-multiplex system

Semiconductor memory having a refresh operation cycle and operating at a high speed and reduced power consumption in a normal operation cycle

Method of fabrication of semiconductor integrated circuit device

Semiconductor integrated device and wiring correction arrangement therefor

Special mode control method for dynamic random access memory

Semiconductor integrated device and wiring correction arrangement therefor

Semiconductor integrated circuit device having protective/output elements and internal circuits

Semiconductor memory device

Dual port semiconductor memory having random and serial access modes

Semiconductor memory

Method of making mask pattern data and process for manufacturing the mask

Semiconductor integrated circuit device having output and internal circuit MISFETS

Memory including address registers

Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor

Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor

Method of making mask pattern data and process for manufacturing the mask

Semiconductor integrated circuit device having a first MISFET of an output buffer circuit and a second MISFET of an internal circuit

Semiconductor integrated circuit device having input protective elements and internal circuits

Memory including address registers for increasing access speed to the memory

Memory array with larger memory capacitors at row ends

Semiconductor device with lead structure on principal surface of chip

Sealed stacked arrangement of semiconductor devices

Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor

NGK INSULATORS LTD

Superconducting fault current limiter

Corona control ring having elongated water discharge holes

Method of forming a zinc sleeve on an insulator pin

ISHIHARA MASAMICHI

Method for manufacturing a chip-size double side connection package

Semiconductor chip package with post electrodes

Semiconductor device and fabrication method for same

LAPIS SEMICONDUCTOR CO LTD

Semiconductor device and process for fabricating the same

Semiconductor device and process for fabricating the same

ELPIDA MEMORY INC

Stacked semiconductor device

OKI SEMICONDUCTOR CO LTD

Semiconductor device and process for fabricating the same

KYUSHU INST TECHNOLOGY

Method of manufacturing semiconductor device with electrode for external connection and semiconductor device obtained by means of said method

INVENSAS CORP

Chip-size, double side connection package and method for manufacturing the same

OKI ELECTRIC IND CO LTD

Semiconductor device with double-sided electrode structure and its manufacturing method

TOKYO ELECTRIC POWER CO

Line arrester