USRE37539EExpiredUtilityPatentIndex 72
Sealed stacked arrangement of semiconductor devices
Est. expiryApr 26, 2010(expired)· nominal 20-yr term from priority
Inventors:OGUCHI SATOSHIISHIHARA MASAMICHIITO KAZUYAMURAKAMI GENANJOH ICHIROSAKUTA TOSHIYUKIYAMAGUCHI YASUNORIKASAMA YASUHIROUDAGAWA TETSUMOMOSE EIJIMATSUNO YOUICHISATOH HIROSHINOZOE ATSUSI
H10W 72/522H10W 72/5524H10W 72/50H10W 72/5522H10W 74/00H10W 70/40H10W 72/884H10W 72/5445H10W 72/865H10W 72/5449H10W 90/753H10W 90/756H10W 72/9445H10W 72/932H10W 72/29H10W 72/59H10W 90/00H10W 90/736H10W 72/5525H10W 72/555H10W 72/553H10W 90/811H10W 70/442H10W 70/415G11C 5/02G11C 5/00H10B 12/00G11C 5/06H10W 72/90H10W 72/00
72
PatentIndex Score
12
Cited by
62
References
40
Claims
Abstract
A pair of DRAM chips 1 A and 1 B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3 B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A stacked arrangement of semiconductor devices, comprising:
a first semiconductor device, including
(i) a first semiconductor substrate having a first main surface and a second main surface, opposing said first surface;
(ii) a first row of bonding pads provided in a central portion of said first main surface of said first semiconductor substrate, said first row of bonding pads consisting of at least a first and a second bonding pad; and
(iii) a first lead electrically connected to said first bonding pad and arranged over said first main surface at one side of said first row of bonding pads, and a second lead electrically connected to said second bonding pad and arranged over said first main surface at the other side of said first row of bonding pads, and
a second semiconductor device, including
(i) a second semiconductor substrate having a first main surface and a second main surface, opposing said first surface;
(ii) a second row of bonding pads having a same bonding pad arrangement as that of said first row of bonding pads and provided in a central portion of said first main surface of said second semiconductor substrate, said second row of bonding pads consisting of at least a third and a fourth bonding pad; and
(iii) a third lead electrically connected to said fourth bonding pad and arranged over said first main surface at one side of said second row of bonding pads, and a fourth lead electrically connected to said third bonding pad and arranged over said first main surface at the other side of said second row of bonding pads,
wherein said first and second semiconductor devices are stacked in a manner such that the second surfaces of said first and second semiconductor substrates are positioned to be facing toward each other, and
wherein said first lead is electrically connected to said fourth lead, and said second lead is electrically connected to said third lead.
2. A stacked arrangement of semiconductor devices according to claim 1 ,
wherein said first and second semiconductor substrates are rectangular shaped and each has a first main surface area defined by a first pair of opposing edge sides and a second, relatively longer pair of opposing edge sides,
wherein said first row and said second row of bonding pads are arrayed along a direction of said second pair of opposing edge sides of said first and second semiconductor substrates, respectively, and
wherein said first and second leads and said third and fourth leads are extended in a direction of said first pair of opposing edge sides of said first and second semiconductor substrates, respectively.
3. A stacked arrangement of semiconductor devices according to claim 2 ,
wherein the stacked arrangement of said first and second semiconductor devices is sealed in a molding resin package.
4. A stacked arrangement of semiconductor devices according to claim 2 ,
wherein said first and second semiconductor substrates, said first and second rows of bonding pads and the electrical connections effected between the first and fourth leads and between the second and third leads are sealed within a molding resin package.
5. A stacked arrangement of semiconductor devices according to claim 4 ,
wherein said molding resin package is rectangle-shaped and is provided with a first group of external leads and a second group of external leads, said first group of external leads and said second group of external leads protrude outwardly from different ones of a pair of opposing outer side surface thereof, said first group of external leads being contiguous with a first group of inner leads provided within the package and said second group of external leads being contiguous with a second of inner leads provided within said package, and
wherein each leads in said first and second group of inner leads is extended inwardly and is contiguous with one of the electrical connections made between one or more bonding pads of said first semiconductor substrate with that of one or more bonding pads of said second semiconductor substrate.
6. A stacked arrangement of semiconductor devices according to claim 5 ,
wherein said pair of opposing outer side surfaces which have said external leads protruding therefrom correspond to those surfaces of the package which are substantially parallel to said second pair of opposing edge sides of said first and second semiconductor substrates in the stacked arrangement.
7. A stacked arrangement of semiconductor devices according to claim 6 ,
wherein said first and second semiconductor substrates constitute first and second semiconductor chips, and
wherein said first row of bonding pads is aligned with said second row of bonding pads, in the stacked arrangement, such that similarly functioning bonding pads are located in the same relative position in both of said first and second semiconductor chips for facilitating an electrical connection between them.
8. A stacked arrangement of semiconductor devices according to claim 7 ,
wherein said first and second semiconductor chips are memory chips.
9. A sealed stacked arrangement of semiconductor devices, comprising:
a first semiconductor device, including
(i) a first rectangle-shaped semiconductor chip having a front surface and a rear surface, and having a first pair of edge sides and a second, longer pair of edge sides;
(ii) a first row of bonding pads, provided at a central portion of said front surface of said first semiconductor chip, being arranged in a direction parallel to the longer edge sides of said first semiconductor chip and consisting of first bonding pads and second bonding pads;
(iii) first leads electrically connected to said first bonding pads, all of said first leads being arranged over said front surface of the first chip, at one side of said first row of bonding pads, and being extended toward one of the pair of longer edge sides thereof; and
(iv) second leads electrically connected to said second bonding pads, all of said second leads being arranged over said front surface of the first chip, at the other side of said first row of bonding pads, and being extended toward the other of the pair of longer edge sides thereof; and
a second semiconductor device, including
(i) a second rectangle-shaped semiconductor chip having a first, front surface and a second, rear surface, and having a first pair of edge sides and a second, longer pair of edge sides;
(ii) a second row of bonding pads having a same bonding pad arrangement as that of said first row of bonding pads and provided at a central portion of said front surface of said second semiconductor chip, said second row of bonding pads being directioned in parallel to the longer edge sides of said second semiconductor chip and consisting of third bonding pads and fourth bonding pads;
(iii) third leads electrically connected to said fourth bonding pads, all of said third leads being arranged over said front surface of the chip, at one side of said second row of bonding pads, and being extended toward one of the pair of longer edge sides thereof; and
(iv) fourth leads electrically connected to said third bonding pads, all of said fourth leads being arranged over said front surface of the second chip, at the other side of said second row of bonding pads, and being extended toward the other of the pair of longer edge sides,
wherein said first and second semiconductor devices are stacked in a manner such that the rear surfaces of said first and second semiconductor chips are positioned so as to be facing toward each other, and
wherein each of said first leads is electrically connected to one of said fourth leads, and each of said second leads is electrically connected to one of said third leads.
10. A sealed stacked arrangement of semiconductor devices according to claim 9 ,
wherein the stacked arrangement of said first and second semiconductor devices is sealed in a molding resin package.
11. A sealed stacked arrangement of semiconductor devices according to claim 9 ,
wherein said first and second semiconductor chips, said first and second rows of bonding pads and the electrical connections effected between said first leads and said fourth leads and between said second leads and said third leads are sealed within a rectangle-shaped molding resin package.
12. A sealed stacked arrangement of semiconductor devices according to claim 11 ,
wherein said rectangle-shaped molding resin package is provided with a first group of external leads and a second group of external leads, said first group of external leads and said second group of external leads protrude outwardly from different ones of a pair of opposing outer side surfaces thereof, said first group of external leads being contiguous with a first group of inner leads provided within the package and said second group of external leads being contiguous with a second group of inner leads provided within said package, and
wherein each lead in said first and second groups of inner leads is extended inwardly and is contiguous with one of the electrical connections made between one or more bonding pads of said first semiconductor chip with that of one or more bonding pads of said second semiconductor chip.
13. A sealed stacked arrangement of semiconductor devices according to claim 12 ,
wherein said pair of opposing outer side surfaces which have said external leads protruding therefrom correspond to those surfaces of the package which are substantially parallel to said second pair of opposing edge sides of said first and second semiconductor chips in the stacked arrangement.
14. A sealed stacked arrangement of semiconductor devices according to claim 13 ,
wherein said first and second semiconductor chips have a similar function and are aligned back-to-back in a manner such that said first row of bonding pads is aligned with said second row of bonding pads, in the stacked arrangement, such that similarly functioning bonding pads are located in the same relative position in both of said first and second chips for facilitating electrical connection between them.
15. A sealed stacked arrangement of semiconductor devices according to claim 14 ,
wherein said first and second semiconductor chips are memory chips.
16. A sealed stacked arrangement of semiconductor devices according to claim 9 ,
wherein said first and second semiconductor chips are memory chips.
17. A semiconductor device, comprising:
a first semiconductor device, including
( i ) a first semiconductor chip having a main surface and a rear surface, opposing said main surface, a plurality of bonding pads being arranged on said main surface;
( ii ) a first lead crossing one side of said first semiconductor chip, a first end portion of said first lead being extended near to said plurality of bonding pads; and
( iii ) a second lead crossing another pads, opposed to said one side of said first semiconductor chip, a first end portion of said second lead being extended near to said plurality of bonding pads;
wherein said first and second leads are electrically connected to corresponding ones of said plurality of bonding pads by wire, respectively,
a second semiconductor device, including
( i ) a second semiconductor chip having a main surface and a rear surface, opposing said main surface, said second semiconductor chip having a same function and a same arrangement of bonding pads as said first semiconductor chip;
( ii ) a third lead crossing one side of said second semiconductor chip, said one side thereof corresponding to said one side of said first semiconductor chip, and a first end portion of said third lead being extended near to said plurality of bonding pads; and
( iii ) a fourth lead crossing another side, opposed to said one side of said second semiconductor chip, a first end portion of said fourth lead being extended near to said plurality of bonding pads,
wherein said third and fourth leads are electrically connected to corresponding ones of said plurality of bonding pads by wire, respectively, and
a molding resin sealing said first and second semiconductor chips which are stacked together,
wherein said first lead and said fourth lead are electrically connected to each other, and said second lead and said third lead are electrically connected to each other.
18. A semiconductor device according to claim 17 , wherein said first semiconductor chip and said second semiconductor chip are stacked so that said main surfaces thereof are facing each other.
19. A semiconductor device according to claim 17 , wherein said first semiconductor chip and said second semiconductor chip are stacked so that said rear surfaces thereof are facing each other.
20. A semiconductor device according to claim 17 , further comprising:
insulating films, said first lead and said second lead being fixedly disposed on said main surface of said first semiconductor chip through one of said insulating films, said third lead and said fourth lead being fixedly disposed on said main surface of said second semiconductor chip through another one of said insulating films.
21. A semiconductor device according to claim 17 ,
wherein said plurality of bonding pads, formed on said first semiconductor chip, are arranged in a row in the spacing separating the first end portions of said first leads from the first end portions of said second leads, and
wherein said plurality of bonding pads, formed on said second semiconductor chip, are arranged in a row in the spacing separating the portion of said third leads from the first end portions of said fourth leads.
22. A semiconductor device according to claim 21 ,
wherein said plurality of bonding pads, formed on said first semiconductor chip, includes a first bonding pad and a second bonding pad, an electrical connection being effected between said first lead and said first bonding pad and between said second lead and said second bonding pad through individual wires, and
wherein said plurality of bonding pads, formed on said second semiconductor chip, includes a first bonding pad and a second bonding pad, said first and second bonding pads thereof having, respectively, the same function as said first and said second bonding pads of said first semiconductor chip, an electrical connection being effected between said third lead and said second bonding pad, of said second semiconductor chip, through said wires, respectively.
23. A semiconductor device according to claim 22 , wherein a first address signal is supplied to said first lead and said fourth lead, and a second, different address signal is supplied to said second lead and said third lead.
24. A semiconductor device according to claim 23 , wherein said first and said second semiconductor chips are memory chips.
25. A semiconductor device according to claim 17 , wherein said first and second leads are protruded from said molding resin.
26. A semiconductor device according to claim 17 , wherein said first, second, third and fourth leads are protruded from said molding resin.
27. A semiconductor device, comprising:
a first semiconductor chip and a second semiconductor chip, each having a plurality of bonding pads arranged on a main surface thereof;
a molding resin which seals a stacked arrangement of said first and said second semiconductor chips;
a plurality of leads, each lead including an inner portion and an outer portion, said outer portion protruding outwardly from said molding resin, and said inner portion branching into a first portion and a second portion in said molding resin; and
a first wire which electrically connects said first portion of the inner portion of a lead to a bonding pad of said first semiconductor chip, and a second wire which electrically connects said second portion of the inner portion of said lead to a bonding pad of said second semiconductor chip,
wherein said first portion of said lead is fixed to said main surface of said first semiconductor chip, and said second portion of said lead is fixed to said main surface of said second semiconductor chip.
28. A semiconductor device according to claim 27 , wherein said first portion of said lead is fixed to said main surface of said first semiconductor chip through an insulating film, and said second portion of said lead is fixed to said main surface of said second semiconductor chip through another insulating film.
29. A semiconductor device according to claim 27 , wherein said first semiconductor ship and said second semiconductor chip have the same bonding pad arrangement.
30. A semiconductor device according to claim 29 , wherein said first semiconductor chip and said second semiconductor chip are stacked so that said main surfaces are facing each other.
31. A semiconductor device according to claim 29 , wherein each of said first and second semiconductor chips has a front, said main surface and an opposing, rear surface, said first semiconductor chip and said second semiconductor chip are stacked so that the rear surfaces are facing each other.
32. A semiconductor device, comprising:
a rectangular - shaped first semiconductor chip having a pad line including a plurality of bonding pads arranged on a main surface thereof, said main surface comprising a first side which is extended along said pad line and a second side which is opposed to said first side,
a rectangular - shaped second semiconductor chip having a pad line including a plurality of bonding pads having the same arrangement, on a main surface thereof, and the same function as the bonding pads of said first semiconductor chip, said main surface comprising a first side and a second chip, corresponding to said first side and said second side of said first semiconductor chip, respectively;
a first lead having a first end portion, said first end portion extending across said first side and being positioned in an area between said pad line and said first side of said first semiconductor chip;
a second lead having a second end portion, said second end portion extending across said second side and being positioned in an area between said pad line and said second side of said second semiconductor chip;
a first bonding wire electrically connecting between said first lead to one of said plurality of bonding pads of said first semiconductor chip, and a second bonding wire electrically connecting said second lead to one of said plurality of bonding pads of said second semiconductor chip; and
a molding resin sealing said first and second semiconductor chips which are stacked to each other,
wherein said first lead and said second lead are electrically connected each other.
33. A semiconductor device according to claim 32 , wherein said first semiconductor chip and said second semiconductor chip are stacked so that said main surfaces are facing each other.
34. A semiconductor device according to claim 32 , wherein each of said first and second semiconductor chips has a front, said main surface and an opposing, rear surface, said first semiconductor chip and said second semiconductor chip are stacked so that said rear surfaces are facing each other.
35. A semiconductor device according to claim 32 , wherein said first and second leads are protruded from said molding resin.
36. A semiconductor device according to claim 32 , wherein one of said first and second leads are protruded from said molding resin.
37. A semiconductor device according to claim 32 , wherein said first lead is fixed to said main surface of said first semiconductor chip through an insulating film, and said second lead is fixed to said main surface of said second semiconductor chip through another insulating film.
38. A composite structure of semiconductor devices, comprising:
a first semiconductor device, including
( i ) a first semiconductor chip having a main surface and a rear surface, opposing said main surface, a plurality of bonding pads being arranged on said main surface;
( ii ) a first lead crossing one side of said first semiconductor chip, a first end portion of said first lead being extended near to said plurality of bonding pads; and
( iii ) a second lead crossing another side, opposed to said one side of said first semiconductor chip, a first end portion of said second lead being extended near to said plurality of bonding pads;
wherein said first and second leads are electrically connected to corresponding ones of said plurality of bonding pads by wire, respectively,
a second semiconductor device, including
( i ) a second semiconductor chip having a main surface and a rear surface, opposing said main surface, said second semiconductor chip having a same function and a same arrangement of bonding pads as said first semiconductor chip;
( ii ) a third lead crossing one side of said second semiconductor chip, said one side thereof corresponding to said one side of said first semiconductor chip, and a first end portion of said third lead being extended near to said plurality of bonding pads; and
( iii ) a fourth lead crossing another side, opposed to said one side of said second semiconductor chip, a first end portion of said fourth lead being extended near to said plurality of bonding pads,
wherein said third and fourth leads are electrically connected to corresponding ones of said plurality of bonding pads by wire, respectively, and
a molding resin sealing said first and second semiconductor chips which are stacked together,
wherein said first lead and said fourth lead are electrically connected to each other, and said second lead and said third lead are electrically connected to each other.
39. A composite structure of semiconductors devices, comprising:
a first semiconductor chip and a second semiconductor chip, each having a plurality of bonding pads arranged on a main surface thereof;
a molding resin which seals a stacked arrangement of said first and said second semiconductor chips;
a plurality of leads, each lead including an inner portion and an outer portion, said outer portion protruding outwardly from said molding resin, and said inner portion branching into a first portion and a second portion in said molding resin; and
a first wire which electrically connects said first portion of the inner portion of a lead to a bonding pad of said first semiconductor chip, and a second wire which electrically connects said second portion of the inner portion of said lead to a bonding pad of said second semiconductor chip,
wherein said first portion of said lead is fixed to said main surface of said first semiconductor chip, and said second portion of said lead is fixed to said main surface of said second semiconductor chip.
40. A composite structure of semiconductor devices, comprising:
a rectangular - shaped first semiconductor chip having a pad line including a plurality of bonding pads arranged on a main surface thereof, said main surface comprising a first side which is extended along said pad line and a second side which is opposed to said first side,
a rectangular - shaped second semiconductor chip having a pad line including a plurality of bonding pads having the same arrangement, on a main surface thereof, and the same function as the bonding pads of said first semiconductor chip, said main surface comprising a first side and a second side, corresponding to said first side and said second side of said first semiconductor chip, respectively;
a first lead having a first end portion, said first end portion extending across said first side and being positioned in an area between said pad line and said first side of said first semiconductor chip;
a second lead having a second end portion, said second end portion extending across said second side and being positioned in an area between said pad line and said second side of said second semiconductor chip;
a first bonding wire electrically connecting between said first lead to one of said plurality of bonding pads of said first semiconductor chip, and a second bonding wire electrically connecting said second lead to one of said plurality of bonding pads of said second semiconductor chip; and
a molding resin sealing said first and second semiconductor chips which are stacked to each other,
wherein said first lead and said second lead are electrically connected each other.Cited by (0)
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