Circuitry and method for clamping a boost signal

Abstract

A clamping circuit clamping a boost signal supplied on a boost line includes a p-channel MOS transistor and an n-channel MOS transistor. These MOS transistors are serially connected between an internal power supply line and the boost line. p-channel MOS transistor receives a clamping level control signal from a clamp control circuit at its gate. In accordance with the clamping level control signal a clamping level given by clamping circuit is varied. Therefore, by decreasing the clamping level of the boost line during an overvoltage-applied mode such as burn-in test, deterioration of components due to an overvoltage can be prevented.

What is claimed is: 
     
       1. A semiconductor device, comprising: a power supply voltage node receiving a power supply voltage;   boosting means for generating on a boost line a boost potential having a level higher than said power supply voltage;   clamping means for restricting an upper limit of the potential on said boost line to the sum of the power supply voltage and one of a plurality of clamping levels; and   clamping level control means for selecting a clamping level of said clamping means.   
     
     
       2. The semiconductor device according to claim 1, further comprising voltage-down means for down-converting an external power supply voltage for generating said power supply voltage, wherein said voltage down means includes determination means for determining whether or not said external power supply voltage is equal to or higher than a predetermined potential level, and wherein   said clamping level control means is responsive to a determination result of said determination means.   
     
     
       3. The semiconductor device according to claim 2, wherein said clamping means provides a first clamping level and a second clamping level lower than said first clamping level, and   said clamping level control means includes means for designating said second clamping level when said determination means indicates that said external power supply voltage is at least at said predetermined potential level.   
     
     
       4. The semiconductor device according to claim 2, wherein said determination means includes; first reference voltage generating means for generating a first reference voltage being constant and independent of said external power supply voltage when said external power supply voltage is at least at a first predetermined value,   second reference voltage generating circuit for generating a second reference voltage changing with said external power supply voltage, when said external power supply voltage is at least at a second predetermined value, and   comparing means comparing said first reference voltage and said second reference voltage.   
     
     
       5. The semiconductor device according to claim 1, wherein said clamping means includes;   a diode-connected first insulating gate-type field effect transistor connected to said boost line, and   a second insulating gate-type field effect transistor connected between said first insulating gate-type field effect transistor and said power supply voltage node, and   said clamping level control means includes means for selectively setting a potential of a gate electrode of said second insulating gate-type field effect transistor.   
     
     
       6. The semiconductor device according to claim 5, wherein said first insulating gate-type field effect transistor includes an n-channel transistor, and said second insulating gate-type field effect transistor includes a p-channel transistor. 
     
     
       7. The semiconductor device according to claim 1, further comprising voltage-down means for down-converting the external power supply voltage for generating a power supply voltage, wherein said clamping level control means includes means for rendering active a clamping level control signal when said external power supply voltage is equal to or higher than a first predetermined value, and for rendering inactive said clamping level control signal a predetermined time after said external power supply voltage is at said first predetermined value or less when said external power supply voltage changes from a level of said first predetermined value or more to a level of said first predetermined value or less, and wherein   said clamping means provides a first clamping level when said clamping level control signal is inactive and provides a second clamping level lower than said first clamping level when said clamping level control signal is active.   
     
     
       8. The semiconductor device according to claim 1, wherein said clamping level control means includes means for rendering active a clamping level control signal when said power supply voltage is at least at a first level, and for rendering inactive said clamping level control signal when said power supply voltage changes from said first level to a second level lower than said first level, and wherein   said clamping means provides a first clamping level when said clamping level control signal is inactive, and provides a second clamping level lower than said first clamping level when said clamping level control signal is active.   
     
     
       9. The semiconductor device according to claim 8, wherein said clamping level control means further includes; voltage dividing means resistively dividing said power supply voltage,   first comparing means for comparing an output of said voltage dividing means and a first reference voltage,   second comparing means for comparing an output of said voltage dividing means and a second reference voltage higher than said first reference voltage, and logically inverting and outputting the result of comparison, and   a flipflop receiving an output of said first comparing means and an output of said second comparing means, respectively, at one and another inputs thereof.   
     
     
       10. The semiconductor device according to claim 1, wherein said clamping means includes;   a diode-connected n-channel MOS transistor connected to said boost line, and   a p-channel MOS transistor connected between said n-channel MOS transistor and said power supply voltage node, and   said clamping level control means includes;   voltage dividing means for resistively dividing said power supply voltage,   first comparing means receiving an output of said voltage dividing means at a positive input thereof and a first reference voltage at a negative input thereof,   second comparing means receiving the output of said voltage dividing means at a positive input thereof and a second reference voltage higher than said first reference voltage at a negative input thereof,   inverting means for logically inverting an output of said second comparing means,   a first NAND gate receiving an output of said inverting means at one input, and   a second NAND gate receiving an output of said first comparing means at one input, and an output of said first NAND gate at another input for applying that output to another input of said first NAND gate, said second NAND gate having an output applied to a gate of said p-channel MOS transistor.   
     
     
       11. The semiconductor device according to claim 1, further comprising: voltage-down means for down-converting an external power supply voltage higher than said power supply voltage for generating said power supply voltage,   first reference voltage generating means for generating a first reference voltage having a constant potential level independent of said external power supply voltage,   second reference voltage generating means for generating a second reference voltage changing depending on said external power supply voltage,   differential amplifying means receiving said first reference voltage at a positive input thereof and said second reference voltage at a negative input thereof, and wherein   said clamping means includes   a diode-connected n-channel MOS transistor connected to said boost line,   a p-channel MOS transistor connected between said n-channel MOS transistor and said power supply voltage node, and   said clamping level control means includes;   control signal generating means for generating a control signal falling to a low level in response to a transition of an output of said differential amplifying means from a high level to a low level, and rising from the low level to the high level after a predetermined time after rising of the output of said differential amplifying means from the low level to the high level, for applying the control signal to a gate of said p-channel MOS transistor.   
     
     
       12. The semiconductor device according to claim 11, wherein said differential amplifying means operates using said external power supply voltage as one operating power supply voltage, and said control signal generating means includes; level converting means for converting a high level of the output of said differential amplifying means to said power supply voltage level,   timer means operating with said power supply voltage as an operating power supply voltage for delaying rising of an output of said level converting means from a low level to a high level by a predetermined time period, and   output means for producing an logical product of the output of said level converting means and an output of said timer means for generating said control signal.   
     
     
       13. The semiconductor device according to claim 12, wherein said timer means includes; a first capacitor means,   inverting means for inverting in logic a charging potential of said capacitor means,   gate means for passing a clock signal having a predetermined period when the output of said level converting means is at the high level,   charging means responsive to an output of a low level of said level converting means for charging said first capacitor means, and   charge pumping means responsive to an output of said gate means for discharging a charging potential of said first capacitor means by charge pumping operation.   
     
     
       14. A semiconductor device, comprising: an external power supply voltage node receiving an external power supply voltage;   a power supply voltage-down means for down-converting the external power supply voltage from said external power supply voltage node for generating an internal power supply voltage and an internal power supply voltage node;   boosting means receiving the internal power supply voltage from said internal power supply voltage node for outputting a boost potential higher than said internal power supply voltage on a boost line, and   clamping means for restricting an upper limit of the potential of said boost line to the sum of the internal power supply voltage and one of a plurality of clamping levels.   
     
     
       15. A semiconductor device, comprising: clamp control means for rendering active a clamping level control signal when a power supply voltage is at least at a first voltage level during an increase of said power supply voltage, and for rendering inactive said clamping level control signal a predetermined time after said power supply voltage attains said first voltage or less during a decrease of said power supply voltage; and   clamping means connected to a boost line boosted to a voltage higher than said power supply voltage and responsive to the clamping level control signal from said clamp control means, for restricting an upper limit of the potential said boost line to the sum of the power supply voltage and one of a plurality of clamping levels, said clamping means including means for selecting a prescribed clamping level and for decreasing said prescribed clamping level when the clamping level control signal from said clamp control means is rendered active.   
     
     
       16. A semiconductor device, comprising: clamp control means for rendering active a clamping level control signal when a power supply voltage is at least at a first voltage during an increase of a power supply voltage, and for rendering said clamping level control signal inactive when said power supply voltage attains a second voltage lower than said first voltage or less during a decrease of said power supply voltage; and   clamping means connected to a boost line boosted to a voltage higher than said power supply voltage and responsive to the clamping level control signal from said clamp control means for restricting an upper limit of the potential of said boost line to the sum of the power supply voltage and one of a plurality of clamping levels, said clamping means including means for selecting a prescribed clamping level and for decreasing said prescribed clamping level when the clamping level control signal from said clamp control means is rendered active.   
     
     
       17. A method for clamping a voltage on a boost line on which a boost signal having a voltage level higher than a power supply voltage supplied to a power supply voltage node is transmitted, comprising the steps of: clamping an upper limit of a voltage of said boost line to first level during an overvoltage-applied mode of operation when a voltage applied to said power supply voltage node is set to a voltage higher than that in a normal operation mode; and   clamping an upper limit of the voltage of said boost line to a second level when the voltage supplied to said power supply voltage node is equal to the voltage supplied thereto during the normal operation mode,   so that a difference between said first level and said power supply voltage is less than that between said second level and said power supply voltage.   
     
     
       18. The semiconductor device according to claim 1, wherein said plurality of clamping levels include a first clamping level and a second clamping level lower than said first clamping level, and said clamping level control means includes means for selecting said second clamping level when an operation mode in which said power supply voltage is made higher than in a normal operation mode is designated. 
     
     
       19. A semiconductor device to which is applied a power supply voltage of a first level for operating said semiconductor device in a normal operating mode and to which is applied a power supply voltage of a second level greater than the first level for operating the semiconductor device in a test operating mode, the semiconductor device comprising: a power supply voltage node for receiving the power supply voltage of the first or second level;   boosting means for applying on a boost line a boost potential of a level higher than the level of the power supply voltage applied on said power supply voltage node;   clamping means for restricting an upper limit of the potential of boost line to the sum of the power supply voltage and one of a plurality of clamping levels; and   clamping control means, responsive to a signal for operating said semiconductor device in the test mode for selecting a clamping level of said clamping means.   
     
     
       20. The device of claim 19, wherein said test operating mode corresponds to a burn-in test of said semiconductor device. 
     
     
       21. The device of claim 19, wherein said upper limit is higher than a level of the power supply voltage applied to said power supply voltage node. 
     
     
       22. A semiconductor device comprising: a power supply voltage node receiving a power supply voltage;   a boost node receiving a boosted voltage higher than the voltage on said power supply voltage node,   an n channel insulated gate transistor having one conduction terminal and a control gate connected together to said boost node, and another conduction terminal;   a p channel insulated gate type transistor having one conduction terminal coupled to the other conduction terminal of said n channel insulated gate type transistor, another conduction terminal coupled to said power supply voltage node, and a control gate receiving a mode control signal having a high level of said voltage on said power supply voltage node and a low level of a ground level, such that the boost node is clamped at levels above the level of said power supply voltage.