Method for manufacturing an insulated gate semiconductor device

Abstract

Insulated gate semiconductor device (10) and a method of manufacturing the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) includes an N-channel transistor (15) and a P-channel transistor (16). The N-channel transistor (15) has a gate electrode (35) that has a central portion (28) and two adjacent gate extensions (49, 52). Likewise the P-channel transistor (16) has a gate electrode (35') which has a central portion (29) and two adjacent gate extensions (53, 54). The gate extensions (49, 52, 53, 54) allow the formation of graded channel regions underneath the gate electrodes (35, 35') and adjacent to the source (57, 59) and drain (58, 62) regions by offsetting an LDD or a single heavily doped source/drain implant from channel regions which are covered by the gate extensions (49, 52 53, 54).

We claim: 
     
       1. A method for manufacturing an insulated gate semiconductor device, comprising the steps of: providing a semiconductor substrate of a first conductivity type and having a major surface;   forming a first layer of dielectric material on a portion of the major surface;   forming a gate electrode on a portion of the first layer of dielectric material by: forming a gate extension layer on the first layer of dielectric material;   forming a second layer of dielectric material on the gate extension layer;   forming an opening in the second layer of dielectric material and the gate extension layer;   filling the opening with a conductive material, wherein a portion of the conductive material filling the opening serves as a first portion of the gate electrode;   removing the second layer of dielectric material;     forming a first spacer adjacent a first side of the first portion of the gate electrode and a second spacer adjacent a second side of the first portion of the gate electrode, wherein the first spacer covers a first portion of the gate extension layer and the second spacer covers a second portion of the gate extension layer, the first and second portions of the gate extension material serving as second and third portions of the gate electrode, respectively; and removing uncovered portions of the gate extension layer to form the second portion of gate electrode adjacent a first side of the first portion of the gate electrode and the third portion of the gate electrode adjacent a second side of the first portion of the gate electrode;     forming at least one dopant region of the first conductivity type after the step of removing the second layer of dielectric material wherein the at least one dopant region of the first conductivity type is aligned to the first side of the first portion of the gate electrode and extends into the semiconductor substrate;   forming first and second dopant regions of a second conductivity type, wherein the first dopant region of the second conductivity type is aligned to a side of the second portion of the gate electrode and extends into the semiconductor substrate and the second dopant region of the second conductivity type is aligned to a side of the third portion of the gate electrode and extends into the semiconductor substrate;   forming first and second electrodes, the first electrode in contact with the first dopant region of the second conductivity type and the second electrode in contact with the second dopant region of the second conductivity type; and   forming a contact to the gate electrode.   
     
     
       2. The method of claim 1, wherein the step of forming a gate extension layer of the first layer of dielectric material includes forming a third layer of dielectric material which serves as the gate extension material. 
     
     
       3. The method of claim 2, wherein the third layer of dielectric material comprises silicon nitride and the second layer of dielectric material comprises oxide. 
     
     
       4. The method of claim 2, wherein the step of filling the opening with a conductive material includes filling the opening with a conductive material comprising polysilicon. 
     
     
       5. The method of claim 1, wherein the step of forming at least one dopant region of the first conductivity type includes implanting an impurity material of the first conductivity type through the gate extension layer second. 
     
     
       6. The method of claim 1, wherein the step of forming a gate extension layer of the first layer of dielectric material includes forming a layer of semiconductor material on the first layer of dielectric material, the layer of semiconductor material serving as the gate extension layer. 
     
     
       7. A method for fabricating an insulated gate semiconductor device, comprising the steps of: providing a semiconductor substrate of a first conductivity type and having a major surface;   forming a first layer of dielectric material on a portion of the major surface;   depositing a material for extending a gate electrode on the first layer of dielectric material;   forming a second layer of dielectric material on the material for extending the gate electrode;   forming a cavity in material deposited for extending the gate electrode;   filling the cavity with a gate electrode material to form a first portion of a gate electrode, the first portion having first and second sides;   removing the second layer of dielectric material;   forming a first spacer adjacent the first side of the first portion of the gate electrode and a second spacer adjacent the second side of the first portion of the gate electrode wherein portions of the material for extending the gate electrode are exposed;   removing the exposed portions of the material for extending the gate electrode to form first and second gate electrode extensions;   doping a first portion of the semiconductor substrate with an impurity material of the first conductivity type, the first portion aligned to the first side of the first portion of the gate electrode;   doping a sub-portion of the first portion of the semiconductor substrate and a second portion of the semiconductor substrate with an impurity material of a second conductivity type, the sub-portion aligned to a side of the first gate electrode extension and the second portion of the semiconductor substrate aligned to a side of the second gate electrode extension;   forming first and second electrodes, the first electrode in contact with the sub-portion of the first portion of the semiconductor substrate and the second electrode in contact with the second portion of the semiconductor substrate; and   forming a contact to the gate electrode.   
     
     
       8. The method of claim 7, wherein the step of depositing a material for extending a gate electrode includes depositing polysilicon. 
     
     
       9. The method of claim 8, wherein the steps of forming a cavity, filling the cavity, and forming spacers include laterally extending the cavity into the material for extending the gate electrode and exposing a portion of the first layer of dielectric material, filling the cavity with polysilicon which serves as a first portion of the gate electrode, isotropically etching the second layer of dielectric material to expose a side of the first portion of the gate electrode, forming the spacer adjacent the exposed side of the gate electrode, wherein portions of the material for extending the gate electrode between the spacer and the first layer of dielectric material serve as a second portion of the gate electrode. 
     
     
       10. The method of claim 7, wherein the step of forming a cavity in the second layer of dielectric material includes forming the cavity in a portion of the material for extending the gate electrode, wherein a portion of the cavity in the portion of the material for extending the gate electrode extends between the first layer of dielectric material and the second layer of dielectric material. 
     
     
       11. The method of claim 7, wherein the step of doping a first portion of the semiconductor substrate with an impurity material of the first conductivity type further includes doping a third portion of the semiconductor substrate with the impurity material of the first conductivity type. 
     
     
       12. A method for manufacturing an insulated gate semiconductor device, comprising the steps of: providing a semiconductor substrate of a first conductivity type and having a major surface;   forming a first layer of dielectric material on a portion of the major surface;   forming a gate electrode on a portion of the first layer of dielectric material by: forming a second layer of dielectric material on the first layer of dielectric material;   forming a third layer of dielectric material on the second layer of dielectric material, wherein the third layer of dielectric material is different from the second layer of dielectric material;   forming a cavity in the third layer of dielectric material and the second layer of dielectric material, wherein the cavity exposes a first portion of the first layer of dielectric material and extends between the third layer of dielectric material and at least a second portion of the first layer of dielectric material;   filling the cavity with a conductive material, wherein a portion of the conductive material filling the cavity serves as a first portion of the gate electrode;   removing the third layer of dielectric material, thereby forming the gate electrode comprising a second portion of the gate electrode adjacent a first side of the first portion of the gate electrode and a third portion of the gate electrode adjacent a second side of the first portion of the gate electrode;   forming at least one dopant region of the first conductivity type, wherein the at least one dopant region of the first conductivity type is aligned to the first side of the first portion of the gate electrode and extends into the semiconductor substrate;   forming first and second dopant regions of a second conductivity type, wherein the first dopant region of the second conductivity type is aligned to a side of the second portion of the gate electrode and extends into the semiconductor substrate and the second dopant region of the second conductivity type is aligned to a side of the third portion of the gate electrode and extends into the semiconductor substrate;   forming first and second electrodes, the first electrode in contact with the first dopant region of the second conductivity type and the second electrode in contact with the second dopant region of the second conductivity type; and   forming a contact to the gate electrode.     
     
     
       13. The method of claim 12, wherein the step of forming a cavity includes laterally removing at least a portion of the second layer of dielectric material.