Nonvolatile semiconductor memory device

Abstract

The present invention provides an electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM) with NAND structured cells which is capable of reducing the number of peripheral circuits required to drive each memory block. The EEPROM according to the present invention includes memory blocks having transfer transistors controlled by a memory block selection signal, wherein the transfer transistors serve as a path through which control gate driving signals are supplied, and wherein control gate driving signals are applied to word lines at full voltage due to a self-boosting operation of each transfer transistor.

What is claimed is: 
     
       1. An electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM) comprising: two or more memory blocks each having two or more NAND cell strings connected between a bit line and a ground voltage via string selection means and ground selection means, respectively,   each of said two or more NAND cell strings including a predetermined number of memory cells having their channels serially connected to one another and their gate terminals controlled by word lines commonly connecting said two or more NAND cell strings, wherein each of said memory cells includes a control gate and a floating gate, and wherein said word lines, control gate, and floating gate each receive control gate driving signals via channels of corresponding transfer transistors,   block selection logic for generating a block selection signal which selects between said two or more memory blocks, and   control gate driving logic for generating control gate driving signals and applying the control gate driving signals to the two or more memory blocks, characterized in that:   gates of said transfer transistors are connected to a common control node, and said block selection signal is applied to said common control node.   
     
     
       2. An electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM) comprising: two or more memory blocks each having two or more NAND cell strings connected between a bit line and a ground voltage via string selection means and ground selection means, respectively,   each of said two or more NAND cell strings including a predetermined number of memory cells having their channels serially connected to one another and their gate terminals controlled by word lines commonly connecting said two or more NAND cell strings, wherein each of said memory cells includes a control gate and a floating gate, and wherein said word lines, control gate, and floating gate each receive control gate driving signals via channels of corresponding transfer transistors,   block selection logic for generating a block selection signal which selects between said two or more memory blocks, and   control gate driving logic for generating control gate driving signals and applying the control gate driving signals to the two or more memory blocks, characterized in that:   said control gate driving logic commonly supplies a string selection signal and a ground selection signal to each one of said two or more memory blocks;   gates of said transfer transistors are connected to a common control node; and,   said block selection signal is applied to said common control node.   
     
     
       3. An electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM), comprising: a plurality of memory blocks, each memory block comprising a plurality of NAND cell strings, a floating gate, and a control gate, each NAND cell string being connected between a bit line and a ground voltage;   a plurality of transfer transistors for controlling the plurality of NAND cell strings, the floating gate, and the control gate in each memory block;   block selection logic for generating a block selection signal to select one of the plurality of memory blocks; and   control gate driving logic for commonly providing control gate driving signals to the plurality of memory blocks,   wherein gates of the transfer transistors are connected to a common node and a source of each of the transfer transistors is connected to each of the control gate driving signals, and the block selection signal is applied to the common control node.   
     
     
       4. An electrically erasable and programmable nonvolatile semiconductor memory device, as in claim 3, wherein each of the plurality of NAND cell strings comprises a plurality of memory cells having their channels serially connected to one another and their gate terminals controlled by word lines commonly connecting the plurality of NAND cell strings. 
     
     
       5. An electrically erasable and programmable nonvolatile semiconductor memory device, as in claim 4, wherein the control gate driving signals are sent over the word lines via the plurality of transfer transistors to control the NAND cell strings. 
     
     
       6. An electrically erasable and programmable nonvolatile semiconductor memory device, as in claim 3, wherein the two or more NAND cell strings are each connected to the bit line via a string selection means and are connected to the ground voltage via a ground selection means, and   wherein the control gate driving signals comprise a string selection signal for operating the string selection means and a ground selection signal for operating the ground selection means.   
     
     
       7. An electrically erasable and programmable nonvolatile semiconductor memory device, as in claim 3, wherein the transfer transistors each include a gate-to-source junction capacitance, and whereby unselected word lines of the memory block are charged through the gate-to-source junction capacitance to a voltage higher than a supply voltage in response to a supply of the control gate driving signals corresponding to the unselected word lines.