Field effect transistor structure of a diving channel device

Abstract

This invention describes a diving channel device structure and a method of forming the diving channel device structure using deep vertical trenches formed in a silicon substrate crossing shallow vertical trenches formed in the same silicon substrate. The deep vertical trenches are filled with a first heavily doped polysilicon to form the sources and drains of field effect transistors. The shallow vertical trenches are filled with a second highly doped polysilicon to form the gates of the transistors. The device structure provides reduced drain and source resistance which remains nearly constant when the device is scaled to smaller dimensions. The device structure also provides reduced leakage currents and a plane topography. The device structure forms a large effective channel width when the device is scaled to smaller dimensions.

What is claimed is: 
     
       1. A diving channel device, comprising: a semiconductor substrate;   deep vertical trenches having deep walls and deep bottoms formed in said semiconductor substrate;   a first dielectric layer formed on said deep bottoms and the lower part of said deep walls of said deep vertical trenches;   a first heavily doped polysilicon material filling said deep vertical trenches;   shallow vertical trenches having shallow walls and shallow bottoms formed in said semiconductor substrate crossing said deep vertical trenches such that said shallow bottoms of said shallow vertical trenches are above the top of said first dielectric layer on said deep walls of said deep vertical trenches;   a second dielectric layer covering said shallow walls and said shallow bottoms of said shallow vertical trenches;   a second heavily doped polysilicon material filling said shallow vertical trenches; and   electrical contacts formed to said first heavily doped polysilicon material and to said second heavily doped polysilicon material.   
     
     
       2. The diving channel device of claim 1 wherein said semiconductor substrate is P type silicon and said first polysilicon material is heavily doped N type polysilicon. 
     
     
       3. The diving channel device of claim 1 wherein said semiconductor substrate is N type silicon and said first polysilicon material is heavily doped P type polysilicon. 
     
     
       4. The diving channel device of claim 1 wherein said deep vertical trenches are between about 0.1 and 1.0 microns wide and between about 0.5 and 5.0 microns deep. 
     
     
       5. The diving channel device of claim 1 wherein the minimum distance between adjacent said deep walls of adjacent said deep vertical trenches is about 0.2 microns. 
     
     
       6. The diving channel device of claim 1 wherein said shallow vertical trenches are between about 0.4 and 2.0 microns deep. 
     
     
       7. The diving channel device of claim 1 wherein the minimum distance between adjacent said shallow walls of adjacent said shallow vertical trenches is about 0.2 microns. 
     
     
       8. The diving channel device of claim 1 wherein the minimum distance between said top of said first dielectric layer on said deep walls of said deep vertical trenches and said shallow bottoms of said shallow vertical trenches is about 0.05 microns. 
     
     
       9. The diving channel device of claim 1 wherein said first dielectric material is silicon dioxide with a thickness between about 200 Angstroms and 600 Angstroms. 
     
     
       10. The diving channel device of claim 1 wherein said second dielectric material is silicon dioxide with a thickness between about 50 and 200 Angstroms. 
     
     
       11. The diving channel device of claim 1 wherein a region adjacent to said shallow walls of Said shallow vertical trenches between adjacent said deep vertical trenches and a region under the shallow bottoms of said shallow vertical trenches between adjacent said deep vertical trenches form the channel region, and the second polysilicon material filling said shallow vertical trenches form the control gates of field effect transistors. 
     
     
       12. The diving channel device of claim 11 wherein the channel width of said field effect transistors is twice the depth of said shallow vertical trenches plus the width of said shallow vertical trenches. 
     
     
       13. The diving channel device of claim 11 wherein said deep vertical trenches form the sources and drains of said field effect transistors, and said first polysilicon material filling said deep vertical trenches can be replaced by other conducting material.