System and method for testing a clock signal

Abstract

The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop ("PLL") circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period. In both cases, if the number of cycles counted is not what was expected, then it is known that the sense clock signal was not properly produced by the PLL circuit.

What is claimed is: 
     
       1. A system for testing a clock signal generator in a data processing system, said system comprising: means for receiving a clock signal;   means for counting a number of cycles of said clock signal occurring in a predetermined period of time; and   means for outputting said number of cycles of said clock signal occurring in said predetermined period of time, wherein said means for counting a number of cycles of said clock signal occurring in a predetermined period of time further comprises:   an AND logic circuit coupled to said receiving means at one input of said AND logic circuit, another input of said AND logic circuit receiving a reference signal dependent upon said predetermined period of time; and   a plurality of scannable shift registers coupled to an output of said AND logic circuit, said plurality of scannable shift registers receiving said reference signal.   
     
     
       2. A method of testing an accuracy of a generated clock signal in a data processing system, said method comprising the steps of: receiving a clock signal from said data processing system;   counting a number of cycles of said clock signal occurring in a predetermined period of time; and   outputting said number of cycles of said clock signal occurring in said predetermined period of time, wherein said step of counting said number of cycles of said clock signal occurring in said predetermined period of time further comprises the steps of performing an AND logical operation of said clock signal and an enable signal, and inputting a resulting signal from said AND logical operation into a plurality of scannable shift registers.   
     
     
       3. The method as recited in claim 2, wherein said enable signal is proportional to said predetermined period of time. 
     
     
       4. A computer system comprising: a memory device, an input/output device, and a display device coupled via a bus to a processor, wherein said processor is embodied on a single chip that includes:   a clock signal generator generating a first clock signal;   a phase locked loop circuit receiving said first clock signal and outputting a second clock signal corresponding to said first clock signal; and   a test circuit comprising: an XOR circuit receiving said first and second clock signals;   a MUX circuit having a first input coupled to an output of said XOR circuit, said MUX circuit having a second input receiving said second clock signal, said MUX circuit including a means for selecting between said first and second inputs for output;   an AND circuit having a first input coupled to said MUX circuit, and a second input receiving an enable signal corresponding to said first clock signal; and   a plurality of shift registers coupled to an output of said AND circuit and receiving said enable signal.