Semiconductor memory device

Abstract

A semiconductor memory device comprises a memory cell array including a plurality of memory cells, each having a data storage capacitor and a MOS transistor, arranged in rows and columns, a plurality of word lines connected to the memory cells in a direction of the rows, a row decoder for decoding a row address signal synchronized with a /RAS signal for selecting one of the word lines corresponding to an arbitrary one of the rows, a plurality of sense amplifiers, provided to have the same number as the number of the columns, for sensing data read out from the memory cells, a plurality of transfer gates connected to the sense amplifiers, a plurality of data latch circuits connected to the transfer gates, to latch the data sensed by the sense amplifiers through the transfer gates, a plurality of column selection gates connected to the data latch circuits for selecting at least one of the data latch circuits, a column decoder for decoding a column address signal for selecting an arbitrary one of the columns to switch-control the column selection gates, and a row controller controlling the row decoder to activate the one of the word lines and inactivate the same at a pre-determined timing which falls within the period after the sense amplifiers are stabilized in an activated state and before the /RAS signal is inactivated.

What is claimed is: 
     
       1. A semiconductor memory device comprising: a memory cell array including a plurality of dynamic memory cells, each having a data storage capacitor and a MOS transistor for an electrical charge transfer gate, arranged in a form of rows and columns;   a plurality of word lines connected to said memory cells of said memory cell array in a direction of said rows;   a row decoder for decoding a row address signal in synchronization with a /RAS signal for selecting one of said word lines corresponding to an arbitrary one of said rows of said memory cell array;   a plurality of sense amplifiers, provided to have the same number as the number of said columns of said memory cell array, for sensing data read out from said memory cells connected to said one of said word lines selected by said row decoder through a plurality of bit lines, respectively;   a plurality of transfer gates connected to said sense amplifiers, respectively;   a plurality of data latch circuits, provided to have the same number as the number of said columns of said memory cell array and connected to said transfer gates, respectively, to latch said data sensed by said sense amplifiers through said transfer gates;   a plurality of column selection gates connected to said data latch circuits, respectively, for selecting at least one of said data latch circuits;   a column decoder for decoding a column address signal for selecting an arbitrary one of said columns of said memory cell array to switch-control said column selection gates; and   a row controller controlling said row decoder so as to activate said one of said word lines selected by said row decoder and sequentially inactivate the same at a predetermined timing, said predetermined timing falling within the period of time after said sense amplifiers are stabilized in an activated state and before said /RAS signal is inactivated.   
     
     
       2. The device according to claim 1, further comprising: an I/O buffer for receiving and transferring I/O data from and to said one of said data latch circuits selected by said column selection gates;   a data bus for connecting said I/O buffer to said column selection gates; and   a load circuit connected between said data bus and a power source.   
     
     
       3. The device according to claim 1, wherein said row controller controls said row decoder in such a manner that said one of said word lines selected by said row decoder is automatically set to be in an inactivated state at the predetermined timing after said one of said word lines is activated, and said sense amplifiers are controlled to start an sensing operation after said one of said word lines is set to be in the activated state, and holds said data until said sense amplifiers are set to be in a precharge state by an outer section after said one of said word lines is inactivated.   
     
     
       4. The device according to claim 2, wherein said row controller controls said row decoder in such a manner that said one of said word lines selected by said row decoder is automatically set to be in an inactivated state at the predetermined timing after said one of said word lines is activated, and said sense amplifiers are controlled to start an sensing operation after said one of said word lines is set to be in the activated state, and holds said data until said sense amplifiers are set to be in a precharge state by an outer section after said one of said word lines is inactivated.   
     
     
       5. The device according to claim 1, wherein said row controller controls said predetermined timing so as to fall within a period of time after said one of said word lines is set to be in the activated state and said sense amplifiers are stabilized in the activated state and before a data transfer from said sense amplifiers to said data latch circuits is started. 
     
     
       6. The device according to claim 2, wherein said row controller controls said predetermined timing so as to fall within a period of time after said one of said word lines is set to be in the activated state and said sense amplifiers are stabilized in the activated state and before a data transfer from said sense amplifiers to said data latch circuits is started. 
     
     
       7. The device according to claim 1, wherein said row controller controls said predetermined timing so as to fall within a period of time after said one of said word lines is set to be in the activated state, said sense amplifiers are stabilized in the activated state and also a data transfer from said sense amplifiers to said data latch circuits is ended, and before said /RAS signal is inactivated. 
     
     
       8. The device according to claim 2, wherein said row controller controls said predetermined timing so as to fall within a period of time after said one of said word lines is set to be in the activated state, said sense amplifiers are stabilized in the activated state and also a data transfer from said sense amplifiers to said data latch circuits is ended, and before said /RAS signal is inactivated. 
     
     
       9. A semiconductor memory device comprising: a memory cell array including a plurality of dynamic memory cells, each having a data storage capacitor and a MOS transistor for an electrical charge transfer gate, arranged in a form of rows and columns;   a plurality of word lines connected to said memory cells of said memory cell array in a direction of said rows;   a row decoder for decoding a row address signal in synchronization with a /RAS signal for selecting one of said word lines corresponding to an arbitrary one of said rows of said memory cell array;   a plurality of sense amplifiers, provided to have the same number as the number of said columns of said memory cell array, for sensing data read out from said memory cells connected to said one of said word lines selected by said row decoder through a plurality of bit lines, respectively;   a plurality of transfer gates connected to said sense amplifiers, respectively;   a plurality of data latch circuits, provided to have the same number as the number of said columns of said memory cell array and connected to said transfer gates, respectively, to latch said data sensed by said sense amplifiers through said transfer gates;   a plurality of column selection gates connected to said data latch circuits, respectively, for selecting at least one of said data latch circuits;   a column decoder for decoding a column address signal for selecting an arbitrary one of said columns of said memory cell array to switch-control said column selection gates; and   a row controller controlling a timing for setting said one of said word lines in the inactivated state to be changed in accordance with whether or not a data transfer from said sense amplifiers, which are stabilized in the activated state, to said data latch circuits is ended before a predetermined first fixed time passes since said one of said word lines selected by said row decoder is activated.   
     
     
       10. The device according to claim 9, further comprising: an I/O buffer for receiving and transferring I/O data from and to said one of said data latch circuits selected by said column selection gates;   a data bus for connecting said I/O buffer to said column selection gates; and   a load circuit connected between said data bus and a power source.   
     
     
       11. The device according to claim 10, wherein when the data transfer from said sense amplifiers to said data latch circuits is not ended before said first fixed time passes since said one of said word lines selected by said row decoder is activated, said row controller controls said row decoder in such a manner that said one of said word lines is automatically set to be in the inactivated state just after said first fixed time passes, and when the data transfer from said sense amplifiers to said data latch circuits is ended before said first fixed time passes since said one of said word lines selected by the said row decoder is activated, said row controller controls said row decoder in such a manner that said one of said word lines is automatically set to be in the inactivated state before said first fixed time passes. 
     
     
       12. The device according to claim 10, wherein said row controller controls a timing of inactivating said one of said word lines automatically before said first fixed time passes so as to be at a time after a predetermined second fixed time passes since said transfer gates are turned off. 
     
     
       13. The device according to claim 11, wherein said row controller controls a timing of inactivating said one of said word lines automatically before said first fixed time passes so as to be at a time after a predetermined second fixed time passes since said transfer gates are turned off. 
     
     
       14. The device according to claim 11, said row controller comprises: a timer circuit receiving said /RAS signal to output a pulse signal having a predetermined time width necessary for setting said first fixed time, which is shorter than a pulse width of said /RAS signal, in synchronization with a front pulse edge of said /RAS signal;   a detecting circuit for detecting whether said transfer gates are turned on or off before said first fixed time passes since said one of said word lines is activated; and   a circuit for controlling said row decoder by outputting a control signal to inactivate said row decoder, whose timing is made same as that of an output signal of said timer circuit when said detecting circuit detects that said transfer gates are turned off.   
     
     
       15. The device according to claim 11, said row controller comprises: a timer circuit receiving said /RAS signal to output a pulse signal having a predetermined time width necessary for setting said first fixed time, which is shorter than a pulse width of said /RAS signal, in synchronization with a front pulse edge of said /RAS signal;   a detecting circuit for detecting whether said transfer gates are turned on or off before said first fixed time passes since said one of said word lines is activated; and   a circuit for controlling said row decoder by outputting a control signal to inactivate said row decoder, whose timing is made faster than that of an output signal of said timer circuit when said detecting circuit detects that said transfer gates are turned on.   
     
     
       16. The device according to claim 11, said row controller comprises: a timer circuit receiving said /RAS signal to output a pulse signal having a predetermined time width necessary for setting said first fixed time, which is shorter than a pulth width of said /RAS signal in synchronization with a front pulse edge of said /RAS signal;   a falling edge delay circuit receiving a transfer gate control signal to delay the falling edge thereof by a predetermined third fixed time, which is longer than said second fixed time;   a first logic circuit receiving an output signal of said falling edge delay circuit and an output signal of said timer circuit to obtain a logical OR therebetween as an output signal thereof;   a falling edge detection circuit receiving said /RAS signal, said transfer gate control signal and an output signal of said timer circuit to detect the falling edge of said transfer gate control signal;   a rising edge delay circuit receiving an output signal of said falling edge detection circuit to delay said falling edge by a predetermined second fixed time; and   a second logic circuit for controlling a passage of said output signal of said first logic circuit using an output signal of said rising edge delay circuit.   
     
     
       17. The device according to claim 1, wherein said column decoder and said row controller perform a pipe-line operation in synchronization with a clock signal from an outer section, said transfer gate control signal is divided into a plurality of subcontrol signals, and said row controller is controlled by said subcontrol signals divided from said transfer gate control signal. 
     
     
       18. The device according to claim 2, further comprising: a transfer gate buffer circuit receiving said transfer gate control signal to output a signal for controlling said row controller and said transfer gate; and   a column address buffer circuit receiving said column address signal to output said column address signal to said column decoder, wherein   said transfer gate buffer circuit, said column address buffer circuit, said row controller, said column decoder, and said I/O buffer are divided into a plurality of stages for performing a pipe-line operation in synchronization with a clock signal from an outer section;   said transfer gate buffer circuit is divided into a plurality of stages including a first stage for controlling said row controller and a second stage for directly controlling said transfer gate in addition to said row controller; and   said row controller controls said row decoder in such a manner that after said one of said word lines selected by said row decoder is activated and a transfer gate control signal in said second stage is temporarily activated before a predetermined first fixed time passes, said one of said word lines is automatically set to be in the inactivated state a predetermined second fixed time later since said transfer gate control signal in said second stage is inactivated.