Method for making a variable length LDD spacer structure

Abstract

A method for making a variable length LDD spacer structure is disclosed. A first insulation layer (i.e., gate oxide) is formed on a semiconductor device having a P-well and an N-well provided in a substrate. A first and a second polysilicon gate are formed on the P-well and the N-well respectively wherein the first insulation layer is interposed between the wells and the gates. A second insulation layer is formed over the first and second gates. N-type impurity ions are selectively implanted to form lightly doped N-type diffusion regions in the P-well. Similarly, P-type impurity ions are selectively implanted to form lightly doped P-type diffusion regions in the N-well. A polysilicon spacer is formed on both side walls of each of the gates. Each spacer covers a portion of the lightly doped N-type and P-type diffusion regions. N-type impurity ions are selectively implanted in a portion of the lightly doped N-type diffusion regions not covered by the spacers. This forms N-type source and drain regions in the P-well adjacent to the lightly doped N-type diffusion regions which have a final length equaling the length of the spacers. Next, the spacers are oxidized or nitridized which enlarges the spacers. P-type impurity ions are selectively implanted in a portion of the lightly doped P-type diffusion regions not covered by the enlarged spacers. This forms P-type source and drain regions in the N-well adjacent to the lightly doped P-type diffusion regions which have a final length equaling the length of the enlarged spacers.

I claim: 
     
       1. A method for fabricating a semiconductor device having a P-well and an N-well provided in a substrate, said method comprising the steps of: (a) forming a first insulation layer on said substrate,   (b) forming a first and a second gate on said P-well and N-well, respectively, with said first insulation layer interposed between said wells and said gates,   (c) forming a second insulation layer over said first and second gates,   (d) implanting impurity ions of an N-type on either side of said first gate so as to form lightly doped N-type diffusion regions in said P-well,   (e) implanting impurity ions of a P-type on either side of said second gate so as to form lightly doped P-type diffusion regions in said N-well,   (f) forming a spacer on both side wails of each of said gates so as to cover a portion of said lightly doped N-type and P-type diffusion regions,   (g) implanting impurity ions of the N-type in a portion of said lightly doped N-type diffusion regions not covered by said spacers so as to form N-type source and drain regions,   (h) oxidizing said spacers so as to enlarge said spacers, and   (i) implanting impurity ions of the P-type in a portion of said lightly doped P-type diffusion regions not covered by said enlarged spacers so as to form P-type source and drain regions,   wherein a final length of each of said lightly doped P-type diffusion regions is aligned with opposing side surfaces, as enlarged in said step of oxidizing, of said respective covering spacer.   
     
     
       2. The method of claim 1 further comprising the steps of: after said step (f), depositing a photoresist layer on the N-well region,   after said step (g), removing said photoresist layer on the N-well region, and   after said step (h), depositing a photoresist layer on the P-well region.   
     
     
       3. The method of claim 1 wherein said first insulation layer is an oxide layer. 
     
     
       4. The method of claim 1 wherein said spacers and said gates are polysilicon. 
     
     
       5. The method of claim 1 wherein said spacers and said gates are polycide. 
     
     
       6. The method of claim 1 wherein a final length of said lightly doped N-type diffusion regions is approximately equal to a length of said spacers prior to said enlarging step. 
     
     
       7. The method of claim 1 wherein a final length of said lightly doped P-type diffusion regions is approximately equal to a length of said enlarged spacers. 
     
     
       8. A method for fabricating a semiconductor device having a PMOS device and an NMOS device which is adjacent to said PMOS device, said method comprising the steps of: (a) implanting impurity ions of an N-type so as to form lightly doped N-type diffusion regions in a substrate of said NMOS device,   (b) implanting impurity ions of a P-type so as to form lightly doped P-type diffusion regions in a substrate of said PMOS device,   (c) forming a spacer on both side wails of a gate of said NMOS device and a gate of said PMOS device so as to cover a portion of said lightly doped N-type and P-type diffusion regions,   (d) implanting impurity ions of the N-type in a portion of said lightly doped N-type diffusion regions not covered by said spacers so as to form N-type source and drain regions for said NMOS device, thereby forming N-LDD regions below said spacers,   (e) oxidizing said spacers so as to enlarge said spacers, and   (f) implanting impurity ions of the P-type in a portion of said lightly doped P-type diffusion regions not covered by said enlarged spacers so as to form P-type source and drain regions of said PMOS device, thereby forming P-LDD regions below said enlarged spacers   wherein a final length of each of said lightly P-LDD regions is aligned with opposing side surfaces, as enlarged in said step of oxidizing, of said respective covering spacer.   
     
     
       9. A method for fabricating a semiconductor device having a PMOS device and an NMOS device, said method comprising the steps of: (a) forming lightly doped drain regions in a substrate for said PMOS and said NMOS devices on either side of a gate of said PMOS device and on either side of a gate of said NMOS device,   (b) forming a spacer on both side walls of said gates so as to cover a portion of said lightly doped drain regions,   (c) forming source and drain regions for said NMOS device in a portion of said lightly doped drain regions which is not covered by said spacers of said NMOS device,   (d) nitridizing said spacers so as to enlarge said spacers, and   (e) forming source and drain regions for said PMOS device in a portion of said lightly doped drain regions which is not covered by said enlarged spacers of said PMOS device   wherein a final length of each of said lightly doped drain regions of said PMOS device is aligned with opposing side surfaces, as enlarged in said step of nitridizing, of said respective covering spacer.   
     
     
       10. A method for fabricating a semiconductor device having a PMOS device and an NMOS device which is adjacent to said PMOS device, said method comprising the steps of: (a) implanting impurity ions of an N-type so as to form lightly doped N-type diffusion regions in a substrate of said NMOS device,   (b) implanting impurity ions of a P-type so as to form lightly doped P-type diffusion regions in a substrate of said PMOS device,   (c) forming a spacer on both side walls of a gate of said NMOS device and a gate of said PMOS device so as to cover a portion of said lightly doped N-type and P-type diffusion regions,   (d) implanting impurity ions of the N-type in a portion of said lightly doped N-type diffusion regions not covered by said spacers so as to form N-type source and drain regions for said NMOS device, thereby forming N-LDD regions below said spacers,   (e) reacting said spacers with an agent so as to enlarge said spacers, and   (f) implanting impurity ions of the P-type in a portion of said lightly doped P-type diffusion regions not covered by said enlarged spacers so as to form P-type source and drain regions of said PMOS device, thereby forming P-LDD regions below said enlarged spacers   wherein a final length of each of said lightly doped P-type diffusion regions is aligned with opposing side surfaces, as enlarged in said step of reacting, said respective covering spacer.   
     
     
       11. A method for fabricating a semiconductor device having a PMOS device and an NMOS device, said method comprising the steps of: (a) forming lightly doped drain regions in a substrate for said PMOS and said NMOS devices on either side of a gate of said PMOS device and on either side of a gate of said NMOS device,   (b) forming a spacer on both side walls of said gates so as to cover a portion of said lightly doped drain regions,   (c) forming source and drain regions for said NMOS device in a portion of said lightly doped drain regions which is not covered by said spacers of said NMOS device,   (d) reacting said spacers with an agent so as to enlarge said spacers, and   (e) forming source and drain regions for said PMOS device in a portion of said lightly doped drain regions which is not covered by said enlarged spacers of said PMOS device   wherein a final length of each of said lightly doped drain regions of said PMOS device is aligned with opposing side surfaces, as enlarged in said step of reacting, of said respective covering spacer.