Device having current ballasting and busing over active area using a multi-level conductor process

Abstract

The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.

What is claimed is: 
     
       1. An integrated circuit device comprising: a semiconductor die;   an insulating layer covering the die having a pattern of etched contact openings for selective contact with conductive layers;   a first conductive layer overlying the insulating layer and making contact to the die through the etched openings in the insulating layer;   a second insulating layer overlying the first conductive layer having a pattern of etched via openings alternating with respect to the pattern of etched contact openings and wherein rows of alternating contacts and vias are staggered with respect to each other; and   a second conductive layer overlying the second insulating layer making contact down to the first conductive layer through the pattern of via openings in the second insulating layer.   
     
     
       2. A device according to claim 1 wherein the alternating pattern of contacts and vias form a plurality of rows. 
     
     
       3. A device according to claim 2 wherein the rows of alternating contacts and vias have spacing between the alternating contacts and vias, whereby areas of maximum conductor thickness is achieved. 
     
     
       4. A semiconductor device comprising: active circuitry formed in a face of semiconductor material;   an insulating layer overlying the active circuitry with openings selectively etched in the insulating layer;   a first conductive layer overlying the insulating layer, the first conductive layer making contact down to the active circuitry through the selective openings in the insulating layer;   a second insulating layer overlying the first conductive layer such that certain portions of the first conductive layer are electrically isolated from each other with selective openings etched in the second insulating layer;   a second conductive layer overlying the second insulating layer making selective contact down to portions of the first conducting layer through the second insulating layer and forming vias such that the second conductive layer is electrically isolated from portions of the first conductive layer and wherein the two conductive layers with contacts and vias from rows of alternating contacts and vias with spacing between the contacts and vias, and wherein the rows of alternating contacts and vias are staggered with respect to one another; and   the second conductive layer forming a bus for the portion of active circuitry contacted through the contacts of the first conductive layer and the vias of the second conductive layer.   
     
     
       5. The semiconductor device of claim 4 wherein the first conductive layer and the second conductive layer are composed of metal. 
     
     
       6. A power integrated circuit device comprising: a lateral MOS transistor disposed on an area of a semiconductor die, the MOS transistor having a plurality of source diffusions, a plurality of drain diffusions, and a plurality of polysilicon gates;   a first insulating layer overlying the MOS transistor with a pattern of openings selectively etched to provide contact down to the plurality of drain diffusions, the plurality of source diffusions, and a plurality of polysilicon gates;   a first conductive layer overlying the first insulating layer making electrical contact down to the plurality of drain diffusions, the plurality of source diffusions, and the plurality of polysilicon gates such that the plurality of drain and source diffusions, and the plurality of polysilicon gates of the MOS power transistor remain electrically isolated from one another;   the first conductive layer making contact to the plurality of polysilicon gates forming a gate contact bus along the periphery of the MOS transistor;   a second insulating layer overlying the first conductive layer having a pattern of etched via openings alternating with respect to the pattern of etched contact openings; and   a second conductive layer overlying the second insulating layer making contact through the vias down to the first conductive layer such that the plurality of source diffusions and the plurality of drain diffusions make electrical contact to the second conductive layer, however, the second conductive layer coupling to the source and the drain of the MOS transistor remain electrically isolated from one another and thus form drain and source contact buses for the MOS transistor whereby die area is conserved and switching performance is improved and wherein the contacts and vias formed in the conductive layers form rows of alternating contacts and vias with spacings between the contacts and vias and wherein the rows of alternating contacts and vias with spacings between them are staggered with respect to one another.   
     
     
       7. An integrated circuit device comprising: active circuitry formed in the face of a semiconductor material with a plurality of transistor devices sharing a common circuit node;   an insulating layer overlying the active circuitry with openings etched in the insulating layer for contact down to the active circuitry;   a conductive layer overlying the insulating layer making contact down to the active circuitry through the contact openings in the insulating layer such that the plurality of transistor devices sharing a common node are making electrical contact and the remaining portions of active circuitry remain electrically isolated from one another;   a second insulating layer overlying the conductive layer with openings etched in the second insulating layer for selective contact down to the conductive layer making electrical contact to the common node of the plurality of transistor devices sharing a common node; and   a second conductive layer overlying the second insulating layer making electrical contact down to the first conductive layer through the etched openings in the second insulating layer thus making electrical contact to the common node of the plurality of transistor devices sharing a common node and becoming the bus for the common node over active circuitry and wherein the contacts and vias on the common node of the plurality of transistor devices sharing a common node have an alternating pattern of contacts and vias in rows with spacings between the contacts and vias, and wherein the rows of alternating contacts and vias with the spacings between the contacts and vias have the rows staggered with respect to one another.