Teos plasma protection technology

Abstract

An improved method of gap filling in the dielectric layer is described. Semiconductor device structures are formed in and on a semiconductor substrate and the top surface of the substrate is planarized. A conducting layer is deposited over the surface of the substrate and patterned. A layer of TEOS oxide is deposited over the patterned conducting layer by plasma enhanced chemical vapor deposition. While TEOS plasma residual remains on the wafer, the oxide is etched wherein the TEOS plasma protects the surface of the oxide layer. The combination of the TEOS deposition and etching processes results in a gap-filling dielectric.

What is claimed is: 
     
       1. A method of manufacturing an integrated circuit device comprising: providing a planarized insulating layer over semiconductor device structures in and on a semiconductor substrate;   depositing a conducting layer overlying said insulating layer and patterning said conducting layer wherein a gap is formed between portions of said patterned conducting layer;   depositing a TEOS oxide layer over the surfaces of said patterned conducting layer;   etching said TEOS oxide layer to open a trench within said TEOS oxide layer over said gap wherein residual TEOS plasma protects the surface of said TEOS oxide from uncontrollable etching; and   wherein said gap is filled by said TEOS oxide layer completing the fabrication of said integrated circuit device.   
     
     
       2. The method according to claim 1 wherein said gap between said portions of said patterned conducting layer is less than about 0.5 microns. 
     
     
       3. The method according to claim 1 wherein said gap is between about 3500 to 8000 Angstroms wide. 
     
     
       4. The method according to claim 1 wherein said TEOS oxide layer is deposited by plasma enhanced chemical vapor deposition at a temperature of between about 250° to 450° C., a TEOS flow rate of between about 400 to 800 sccm, an O 2  flow rate of between about 400 to 800 sccm, and pressure of between about 6 to 9 Torr. 
     
     
       5. The method according to claim 1 wherein said depositing said TEOS oxide layer is performed within a deposition chamber and wherein said etching is performed within said same deposition chamber. 
     
     
       6. The method according to claim 5 wherein said deposition chamber is not pumped down after said depositing said TEOS oxide layer. 
     
     
       7. The method according to claim 4 wherein said etching is performed at said same temperature as said depositing said TEOS oxide layer. 
     
     
       8. The method according to claim 1 wherein said steps of depositing said TEOS oxide and etching are repeated until said gap is filled. 
     
     
       9. The method according to claim 1 further comprising planarizing said TEOS oxide layer by chemical mechanical polishing. 
     
     
       10. The method according to claim 1 further comprising planarizing said TEOS oxide layer by the steps of: coating said TEOS oxide layer with at least one spin-on-glass layer;   baking and curing said at least one spin-on-glass layer; and   etching back said spin-on-glass layer until the surface of said substrate is planarized.   
     
     
       11. A method of forming a gap-filling dielectric layer in the fabrication of an integrated circuit device comprising: providing a conducting layer overlying an insulating layer over a semiconductor substrate and patterning said conducting layer wherein a gap is formed between portions of said patterned conducting layer; and   forming a gap-filling dielectric layer comprising: depositing a TEOS oxide layer over the surfaces of said patterned conducting layer;   etching said TEOS oxide layer to open a trench within said TEOS oxide layer over said gap wherein residual TEOS plasma protects the surface of said TEOS oxide from uncontrollable etching; and   repeating said depositing and said etching steps until said gap is filled by said TEOS oxide layer     completing the formation of said gap-filling dielectric layer in the fabrication of said integrated circuit device.   
     
     
       12. The method according to claim 11 wherein said gap between said portions of said patterned conducting layer is less than about 0.5 microns. 
     
     
       13. The method according to claim 11 wherein said gap is between about 3500 to 8000 Angstroms wide. 
     
     
       14. The method according to claim 11 wherein said TEOS oxide layer is deposited by plasma enhanced chemical vapor deposition at a temperature of between about 250° to 450° C., a TEOS flow rate of between about 400 to 800 sccm, an O 2  flow rate of between about 400 to 800 sccm, and pressure of between about 6 to 9 Torr. 
     
     
       15. The method according to claim 11 wherein said depositing said TEOS oxide layer is performed within a deposition chamber and wherein said etching is performed within said same deposition chamber. 
     
     
       16. The method according to claim 15 wherein said deposition chamber is not pumped down after said depositing said TEOS oxide layer. 
     
     
       17. The method according to claim 14 wherein said etching is performed at said same temperature as said depositing said TEOS oxide layer. 
     
     
       18. A method according to claim 11 further comprising planarizing said TEOS oxide layer by chemical mechanical polishing. 
     
     
       19. A method according to claim 11 further comprising planarizing said TEOS oxide layer by the steps of: coating said TEOS oxide layer with at least one spin-on-glass layer;   baking and curing said at least one spin-on-glass layer; and   etching back said spin-on-glass layer until the surface of said substrate is planarized.   
     
     
       20. The method according to claim 11 wherein said semiconductor substrate includes semiconductor device structures including gate electrodes and source and drain regions. 
     
     
       21. The method according to claim 11 wherein said semiconductor substrate includes semiconductor device structures including gate electrodes and source and drain regions and at least a first level of metallization. 
     
     
       22. The method according to claim 11 wherein said semiconductor substrate includes semiconductor device structures including gate electrodes and source and drain regions and a final level of metallization and further comprising depositing a silicon nitride passivation layer overlying said gap-filling dielectric layer. 
     
     
       23. A method of forming a gap-filling dielectric layer in a single deposition chamber in the fabrication of an integrated circuit device comprising: providing a conducting layer overlying an insulating layer over a semiconductor substrate and patterning said conducting layer wherein a gap is formed between portions of said patterned conducting layer; and   forming a gap-filling dielectric layer comprising: depositing a TEOS oxide layer over the surfaces of said patterned conducting layer within said deposition chamber wherein a high deposition temperature of between about 250° to 450° C. is maintained;   etching said TEOS oxide layer to open a trench within said TEOS oxide layer over said gap wherein residual TEOS plasma within said deposition chamber protects the surface of said TEOS oxide from uncontrollable etching due to said high temperature; and   repeating said depositing and said etching steps until said gap is filled by said TEOS oxide layer     completing the formation of said gap-filling dielectric layer in said single deposition chamber in the fabrication of said integrated circuit device.   
     
     
       24. The method according to claim 23 wherein said gap between said portions of said patterned conducting layer is less than about 0.5 microns. 
     
     
       25. The method according to claim 23 wherein said gap is between about 3500 to 8000 Angstroms wide. 
     
     
       26. The method according to claim 23 wherein said TEOS oxide layer is deposited by plasma enhanced chemical vapor deposition with a TEOS flow rate of between about 400 to 800 sccm, an O 2  flow rate of between about 400 to 800 sccm, and pressure of between about 6 to 9 Torr. 
     
     
       27. The method according to claim 23 wherein said deposition chamber is not pumped down after said depositing said TEOS oxide layer. 
     
     
       28. A method according to claim 23 further comprising planarizing said TEOS oxide layer by chemical mechanical polishing. 
     
     
       29. A method according to claim 23 further comprising planarizing said TEOS oxide layer by the steps of: coating said TEOS oxide layer with at least one spin-on-glass layer;   baking and curing said at least one spin-on-glass layer; and   etching back said spin-on-glass layer until the surface of said substrate is planarized.   
     
     
       30. The method according to claim 23 wherein said semiconductor substrate includes semiconductor device structures including gate electrodes and source and drain regions. 
     
     
       31. The method according to claim 23 wherein said semiconductor substrate includes semiconductor device structures including gate electrodes and source and drain regions and at least a first level of metallization. 
     
     
       32. The method according to claim 23 wherein said semiconductor substrate includes semiconductor device structures including gate electrodes and source and drain regions and a final level of metallization and further comprising depositing a silicon nitride passivation layer overlying said gap-filling dielectric layer.